tag:blogger.com,1999:blog-77118511765159407342024-03-13T03:59:52.828-07:00GE WaferAs a semiconductor wafer manufacturer, PAM-XIAMEN develops advanced crystal growth and epitaxy technologies.powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.comBlogger124125tag:blogger.com,1999:blog-7711851176515940734.post-89051043406101843272020-04-13T18:30:00.002-07:002020-04-13T18:30:20.826-07:00Physical and Electrical Properties of Polycrystalline Si1 − x Ge x Deposited Using Single-Wafer-Type Low Pressure CVD<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #333333;">Polycrystalline (poly) </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn1.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn1.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> films have been suggested as a promising alternative to the currently employed poly silicon gate electrode for complementary metal oxide semiconductor<b> field effect transistor </b>technology due to lower resistivity, less boron penetration, and less gate depletion effect than that of poly Si gates. We investigated the deposition characteristics and physical properties of poly </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn2.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn2.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> films using </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn3.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn3.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> and </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn4.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn4.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> as deposition source gases in single-<b>wafer</b>-type low pressure chemical vapor deposition (LPCVD) system and the <b>electrical properties</b> of </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn5.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn5.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> MOS capacitors with the poly </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn6.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn6.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn7.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn7.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> gate stack. Deposition rate as well as <b>Ge</b> content of poly </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn8.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn8.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> films shows the large increase with the addition of a small fraction of </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn9.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn9.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> while, above critical </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn10.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn10.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> flux, it is slightly changed. In addition, the Ge content in poly </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn11.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn11.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> films decreased with an increase in deposition temperature. The flatband voltage of the poly </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn12.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn12.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> gate stack decreased by 0.3 V and gate depletion effect of poly </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn13.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn13.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> gate stack was reduced by 18% as compared to that of the poly Si gate stack. In addition, the charge to breakdown </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn14.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn14.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> of the poly </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn15.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/1/G13/jes_151_1_G13ieqn15.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> gate stack was higher than that of poly Si gate stack. © 2003 The Electrochemical Society. All rights reserved.</span></span><br />
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powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-42604703700178210582020-04-06T19:16:00.004-07:002020-04-06T19:16:27.057-07:00(Invited) Ge/III-V Heterostructures and Their Applications in Fabricating Engineered Substrates<span style="color: #333333;"><span style="font-family: Arial, Helvetica, sans-serif;">Chip level integration of III-V devices with Si-CMOS platform requires the use of engineered substrates. Fabrication of engineered substrates utilizes technologies such as epitaxy, wafer bonding and layer transfer. We report on two aspects of III-V/IV materials integration developments that are on the path to enabling Ge-on-insulator (<b>GeOI</b>) and GaAs-on-insulator (GaAsOI) on Si substrates without the use of SmartcutTM technology. We report on the establishment of <b>Ge</b>/AlAs/GaAs and GaAs/Ge/GaAs epitaxial structures/sequences with low defect density and surface properties suitable for wafer bonding. The<b> epitaxial</b> structures have embedded layers that offer highly selective etch properties that facilitate lift-off onto Si substrates. We demonstrate the use of these novel Ge/III-V heterostructures to liftoff layers of Ge through an aqueous hydrogen fluoride (HF) based epitaxial lift-off (ELO) process, or layers of GaAs through a gas phased ELO process enabled by xenon difluoride (XeF2) selective etching of Ge.</span></span><br />
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powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-70006181183904797022020-03-29T20:00:00.000-07:002020-03-29T20:00:01.731-07:00Selective Epitaxial Growth of Germanium on Si Wafers with Shallow Trench Isolation: An Approach for Ge Virtual Substrates<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #333333;"><b>Ge</b> selective epitaxial growth (SEG) in shallow trench isolated windows is of great interest in advanced devices due to the good lateral electrical isolation of shallow trenches and the possibility of integrating Ge on Si wafers. However, the <b>high density</b> of threading <b>dislocations </b>in strain-relaxed Ge layers and facet formation are two major concerns in Ge SEG. In this work, we have obtained facet-free growth of Ge in shallow trench isolated Si windows with a threading <b>dislocation density</b> (TDD) of 4.2</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; font-weight: 700; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">×</span><span style="color: #333333;">108 cm-2. A mass transport model is developed to simulate the Ge faceting and the factors influencing the Ge deposition selectivity are studied.</span></span><br />
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powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com1tag:blogger.com,1999:blog-7711851176515940734.post-12395324057934041032020-03-23T23:40:00.001-07:002020-03-23T23:40:06.891-07:00Double intermediate bonding layers for the fabrication of high-quality silicon-on-insulator-based exfoliated Ge film with excellent high-temperature characteristics<span style="color: #333333;"><span style="font-family: Arial, Helvetica, sans-serif;">We investigate the high-temperature characteristics of wafer-bonded silicon-on-insulator (SOI)-based Ge film with two different intermediate bonding layers. For an amorphous Ge (a-Ge) bonding layer, due to the crystallization of a-Ge, many gas bubbles appear at the bonded interface to form <b>Ge</b> pits on the SOI. When the wafer pairs are annealed at ≥400 °C, new gas bubbles appear and merge, leading to cracking of the Ge film due to the fact that the new gas bubbles cannot be transferred sufficiently rapidly out of the bonded interface of two single-crystal materials. For an a-Ge/a-Si bonding layer, the porous a-Si can serve as a reservoir at the bonded interface to absorb the by-products. With increase in a-Si layer thickness, the gas bubble density decreases. New gas bubbles are not observed after annealing at 500 °C when a 30 nm thick a-Si layer is introduced. More importantly, the quality of the Ge film with an a-Ge/a-Si bonding layer significantly improves after post-annealing. This can be explained by the repair of the point defects and restraining of the nucleation of threading dislocations by a-Si (no crystal orientation). This work presents high-quality heterogeneous hybrid integration of photoelectric materials by wafer bonding, which may give guidance for the low-temperature integration of Ge/Si, GeSn/Si and III–V/Si.</span></span><br />
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powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-50853028343352937892020-03-17T19:14:00.001-07:002020-03-20T00:33:57.156-07:00Coplanar Integration of Lattice-Mismatched Semiconductors with Silicon by Wafer Bonding Ge / Si1 − x Ge x / Si Virtual Substrates<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;">We have demonstrated a general process which could be used for the integration of lattice-mismatched semiconductors onto large, Si-sized wafers by wafer bonding </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn1.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn1.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> virtual substrates. The challenges for implementing this procedure for large diameter Ge-on-insulator (GOI) have been identified and solved, resulting in the transfer of epitaxial </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn2.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn2.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> to a Si wafer. We found that planarization of<b> Ge</b> virtual <b>substrates</b> was a key limiting factor in the transfer process. To circumvent this problem, an oxide layer was first deposited on the Ge film before planarization using a standard oxide chemical mechanical planarization process. The GOI structure was created using </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn3.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn3.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;">-induced layer exfoliation (Smartcut™) and a buried </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn4.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn4.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> etch-stop layer, which was used to subsequently remove the surface damage with a hydrogen peroxide selective etch. After selective etching, the crosshatched surface morphology of the original virtual substrate was preserved with roughness of <15 nm rms as measured on a </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn5.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn5.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> scale and a </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn6.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn6.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> scale roughness of </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn7.jpg" src="https://cdn.iopscience.com/images/1945-7111/151/7/G443/jes_151_7_G443ieqn7.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> Using an etch-stop layer, the transferred device layer thickness is defined epitaxially allowing for future fabrication of ultrathin GOI as well as III-V films directly on large-diameter Si wafers. © 2004 The Electrochemical Society. All rights reserved.</span></span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;"><br /></span></span><span style="font-size: x-small;"><span style="color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif;"><span style="font-family: Arial, Helvetica, sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-47713659084937922982020-03-10T23:27:00.000-07:002020-03-20T00:34:06.338-07:00Two-dimensional arrays of nanometre scale holes and nano-V-grooves in oxidized Si wafers for the selective growth of Ge dots or Ge/Si hetero-nanocrystals<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;">Two-dimensional (2D) arrays of nanometre scale holes were opened in thin SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> layers on silicon by electron beam lithography and chemical etching. Oxidized silicon <b>wafers</b> with a 5 nm thick <b>SiO</b></span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;"><b>2</b></span><span style="color: #333333;"> layer on top were used in this respect. Pattern transfer involved either only removal of SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> or a two-step process of oxide removal and anisotropic silicon <b>chemical etching</b> to form <b>nanometre</b> scale silicon V-grooves. The size of the holes in the photoresist layer varied in the range 40–80 nm, depending on the <b>exposure dose </b>used. The smallest holes in the oxide were about 50 nm in diameter, while in V-grooves the smallest width was </span><img align="MIDDLE" alt="{\approx } 70 " data-src="https://cdn.iopscience.com/images/0957-4484/15/11/056/nano184318ieqn1.gif" src="https://cdn.iopscience.com/images/0957-4484/15/11/056/nano184318ieqn1.gif" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> nm. 2D arrays of <b>Ge </b>dots or Ge/Si hetero-nanocrystals were selectively grown on these patterned silicon wafers. In small windows only one Ge island per hole was nucleated.</span></span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;"><br /></span></span><span style="font-size: x-small;"><span style="color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif;"><span style="font-family: Arial, Helvetica, sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-3981323462053041942020-03-05T17:41:00.001-08:002020-03-20T00:34:13.993-07:00High Quality Ge Virtual Substrates on Si Wafers with Standard STI Patterning<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;">Further improving complementary metal oxide semiconductor performance beyond the 22 nm generation likely requires the use of high mobility channel materials, such as Ge for <b>p-type</b> metal oxide semiconductor (<b>pMOS</b>) and III/V for n-type metal oxide semiconductor devices. The complementary integration of both materials on Si substrates can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates using Si wafers with standard shallow trench isolation (STI). This reduces the fabrication cost of these virtual <b>substrates</b> as the complicated isolation scheme in blanket Ge can be omitted. The low topography enables integration of ultrathin high-</span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/157/1/H13/jes_157_1_H13ieqn1.jpg" src="https://cdn.iopscience.com/images/1945-7111/157/1/H13/jes_157_1_H13ieqn1.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> gate dielectrics. The fabrication schemes are also compatible with uniaxial stress techniques. Both modules include an annealing step at </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/157/1/H13/jes_157_1_H13ieqn2.jpg" src="https://cdn.iopscience.com/images/1945-7111/157/1/H13/jes_157_1_H13ieqn2.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> to reduce the threading dislocation densities down to </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/157/1/H13/jes_157_1_H13ieqn3.jpg" src="https://cdn.iopscience.com/images/1945-7111/157/1/H13/jes_157_1_H13ieqn3.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;"> and </span><img align="MIDDLE" alt="" data-src="https://cdn.iopscience.com/images/1945-7111/157/1/H13/jes_157_1_H13ieqn4.jpg" src="https://cdn.iopscience.com/images/1945-7111/157/1/H13/jes_157_1_H13ieqn4.jpg" style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: auto; line-height: inherit; margin: 0px; max-width: 100%; padding: 0px; vertical-align: middle; width: auto;" /><span style="color: #333333;">, respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter are illustrated by preliminary results of selective <b>epitaxial InGaAs</b> growth on virtual <b>Ge substrates</b>.</span></span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;"><br /></span></span><span style="font-size: x-small;"><span style="color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif;"><span style="font-family: Arial, Helvetica, sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-5633427324487381852020-02-25T18:23:00.001-08:002020-03-20T00:34:21.568-07:00Lateral Gemanium Growth for Local GeOI Fabrication<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;">High quality local <b>Germanium</b>-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single <b>wafer</b> reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. By plan view TEM it is shown, that the dislocations in Ge which direct to <b>SiO</b></span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;"><b>2</b></span><span style="color: #333333;"><b> </b>cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to <b>BOX</b> are observed only in [110] or equivalent direction. The resulting Ge grown toward [010] direction contains no dislocations. A root mean square of roughness of ~0.2 nm is obtained after the SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;">.</span></span><br />
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powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-62828916478063991912020-02-19T01:19:00.002-08:002020-03-20T00:34:29.098-07:00The Characteristics of Interface Microstructures in Germanium/SiO2 Low Temperature Wafer Bonding<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;">Ge/SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> direct wafer bonding by O</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;">-plasma pretreatment was investigated. The bonding interfaces of <b>Ge</b>/SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> low temperature direct<b> wafer</b> bonding were characterized by transmission electron microscopy. The perfectly atomic level Ge/SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> bonding was achieved after a 150</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">0</span><span style="color: #333333;">C annealing for 60 hours. The excessive O</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;">-plasma exposure resulted in micro-crack formation close to the bonding interface in Ge. A model involved micro-crack formed in Ge was proposed. Our experiments, for the first time, demonstrated that a perfectly seamless bonding of Ge/SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> by O</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;">-plasma pretreatment depends not only on optimal O</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;">-plasma pretreatment time but also on the manner of the raised annealing temperature to enhance the bonding strength. A slowly ramping rate heating is crucial to accomplish perfectly seamless Ge/SiO</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;"> wafer bonding apart from an optimal O</span><span style="border: 0px; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;">-plasma exposure time chosen.</span></span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;"><br /></span></span><span style="font-size: x-small;"><span style="color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif;"><span style="font-family: Arial, Helvetica, sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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<span style="font-size: x-small;"><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;">For more information, please visit our website: </span><a href="https://www.powerwaywafer.com/" style="box-sizing: border-box; color: #0555b8; font-family: Arial, Helvetica, sans-serif; outline: none !important; text-align: start; text-decoration-line: none;">https://www.powerwaywafer.com</a><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;">,</span><br style="box-sizing: border-box; color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;" /><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;">send us email at </span><a href="mailto:sales@powerwaywafer.com" style="box-sizing: border-box; color: #0555b8; font-family: Arial, Helvetica, sans-serif; outline: none !important; text-align: start; text-decoration-line: none;">sales@powerwaywafer.com</a><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;"> and </span><a href="mailto:powerwaymaterial@gmail.com" style="box-sizing: border-box; color: #0555b8; font-family: Arial, Helvetica, sans-serif; outline: none !important; text-align: start; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></div>
powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-14507059719635516722020-02-12T00:00:00.002-08:002020-03-20T00:34:36.845-07:00(Invited) Device and Integration Technologies of III-V/Ge Channel CMOS<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;">One of the ultimate CMOS structures can be the combination of III-V nMOSFETs and Ge pMOSFETs. In this presentation, we focus on the possible solutions for realizing CMOS integration of III-V and Ge MOSFETs. In order to realize the integration of III-V/Ge MOSFETs, the direct wafer bonding is a promising way. The gate stack formation is also a critical issue for III-V/<b>Ge </b>CMOS integration. We have employed Al2O3 gate insulators for both InGaAs and Ge MOSFETs. We have recently realized Al2O3/GeOx/Ge MOS gate stacks with low Dit and thin EOT by employing ALD Al2O3 and successive plasma oxidation. We consider that metal S/D scheme can be the best solution for III-V/Ge CMOS. We have implemented Ni-based metal S/D technologies for InGaAs and <b>Ge</b> MOSFETs. By employing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.</span></span><br />
<span style="font-size: x-small;"><span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;"><br /></span></span><span style="color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif;"><span style="font-family: Arial, Helvetica, sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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<span style="font-size: x-small;"><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;">For more information, please visit our website: </span><a href="https://www.powerwaywafer.com/" style="box-sizing: border-box; color: #0555b8; font-family: Arial, Helvetica, sans-serif; outline: none !important; text-align: start; text-decoration-line: none;">https://www.powerwaywafer.com</a><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;">,</span><br style="box-sizing: border-box; color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;" /><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;">send us email at </span><a href="mailto:sales@powerwaywafer.com" style="box-sizing: border-box; color: #0555b8; font-family: Arial, Helvetica, sans-serif; outline: none !important; text-align: start; text-decoration-line: none;">sales@powerwaywafer.com</a><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;"> and </span><a href="mailto:powerwaymaterial@gmail.com" style="box-sizing: border-box; color: #0555b8; font-family: Arial, Helvetica, sans-serif; outline: none !important; text-align: start; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></div>
powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-68915260909463671692020-01-20T19:40:00.000-08:002020-03-20T00:34:44.855-07:00Analysis of Trace Levels of Ge Transferred to Si Wafer Surfaces during SiGe Wafer Processing<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;">Effects of trace levels of <b>Ge </b>transferred to Si surfaces during thermal processing of SiGe wafers are presented here. Si wafers were coprocessed in an <b>oxidation furnace</b> with SiGe relaxed graded buffer layers grown on Si. Total <b>X-ray fluorescence</b> measurements on Si wafers showed Ge concentrations in varying degrees depending on <b>oxidation temperature</b>, time, and the number of coprocessed SiGe wafers. The Ge concentration level increases with increase of oxidation time, temperature, and SiGe <b>wafer</b> quantity. It was also observed that the furnace shows "memory" of the process during subsequent process runs. A chlorine-based purge of the oxidation tube after processing SiGe wafers helps reduce the Ge concentration remarkably. Metal oxide semiconductor capacitance and gate leakage characterization were used to evaluate the effects of transferred Ge on the gate oxide. The interface state density is marginally higher on Si wafers with transferred Ge. © 2003 The Electrochemical Society. All rights reserved.</span></span><br />
<span style="background-color: white; color: #333333; font-family: "arial" , "helvetica" , sans-serif; font-size: x-small;"><br /></span><span style="font-size: x-small;"><span style="color: #222222; font-family: Arial, Tahoma, Helvetica, FreeSans, sans-serif;"><span style="font-family: Arial, Helvetica, sans-serif;"><span style="text-align: justify;">Source:IOPscience</span></span></span></span><br />
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<span style="font-size: x-small;"><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;">For more information, please visit our website: </span><a href="https://www.powerwaywafer.com/" style="box-sizing: border-box; color: #0555b8; font-family: Arial, Helvetica, sans-serif; outline: none !important; text-align: start; text-decoration-line: none;">https://www.powerwaywafer.com</a><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;">,</span><br style="box-sizing: border-box; color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;" /><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;">send us email at </span><a href="mailto:sales@powerwaywafer.com" style="box-sizing: border-box; color: #0555b8; font-family: Arial, Helvetica, sans-serif; outline: none !important; text-align: start; text-decoration-line: none;">sales@powerwaywafer.com</a><span style="color: #777777; font-family: Arial, Helvetica, sans-serif; text-align: start;"> and </span><a href="mailto:powerwaymaterial@gmail.com" style="box-sizing: border-box; color: #0555b8; font-family: Arial, Helvetica, sans-serif; outline: none !important; text-align: start; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></div>
powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-5289145827152267082020-01-13T18:50:00.003-08:002020-01-13T18:50:38.625-08:00Room Temperature Bonding of Wafers Using Si and Ge Films with Extremely Low Electrical Conductivity<span style="color: #333333;"><span style="font-family: Arial, Helvetica, sans-serif;">The technical potential of room temperature bonding of wafers in vacuum using amorphous Si (a-Si) and Ge (a-Ge) films was studied. Transmission electron microscopy images revealed no interface corresponding to the original films surfaces for bonded a–Ge–a–Ge films. Analyses of film structure and the surface free energy at the bonded interface revealed higher bonding potential at the connected a–Ge–a–Ge interface than that of a–Si films. The electrical resistivity of a-Ge films is 0.62 Ωm, which is lower than that of a-Si film (4.7 Ωm), but 7–8 order higher than that of representative material films used for bonding in vacuum. Our results indicate that room temperature bonding using a–<b>Ge</b> films is useful to bond wafers without any marked influence on the electrical properties of devices on wafer surfaces caused by the electrical conductivity of films used for bonding.</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><span style="background-color: white; color: #333333;">Source:IOPscience</span><br style="background-color: white; color: #222222;" /><span style="background-color: white; color: #333333;"><br /></span><span style="background-color: white; color: #222222;"></span><span style="background-color: white; color: #333333;">For more information, please visit our website: <a href="http://www.semiconductorwafers.net/" style="color: #888888; text-decoration-line: none;">www.semiconductorwafers.net</a>,</span><br style="background-color: white; color: #222222;" /><span style="background-color: white; color: #333333;">send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #888888; text-decoration-line: none;">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #888888; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-7710134649853720752019-12-25T00:08:00.003-08:002019-12-25T00:08:29.758-08:00(Invited) Significant Enhancement of High-Ns Electron Mobility in Ge n-MOSFETs with Atomically Flat Ge/GeO2 Interface<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #333333;">The rapid degradation of high-</span><i style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">N<span style="border: 0px; font-stretch: inherit; font-style: inherit; font-variant: inherit; font-weight: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">s</span></i><span style="color: #333333;"> electron mobility in Ge n-MOSFETs is still one of the greatest concerns in<b> Ge</b> CMOS technology. Although there are many possible origins so far considered, the degradation mechanism is still unclear in spite of its importance. In this work, we clarify wafer-related origins for electron mobility degradation in Ge n-MOSFETs. High-</span><i style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">N<span style="border: 0px; font-stretch: inherit; font-style: inherit; font-variant: inherit; font-weight: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">s</span></i><span style="color: #333333;"> electron mobility is dramatically improved thanks to (i) atomically flat Ge surface formation, followed by (ii) layer-by-layer oxidation. (iii) Oxygen-related neutral impurities in Ge substrates could be another origin of the mobility reduction on Ge wafers. By successfully eliminating these scattering sources in Ge n-MOSFETs, we demonstrate intrinsically high electron mobility in a wide range of </span><i style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">N<span style="border: 0px; font-stretch: inherit; font-style: inherit; font-variant: inherit; font-weight: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">s</span></i><span style="color: #333333;">.</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><br style="background-color: #fefdfa; color: #333333;" /><span style="background-color: #fefdfa; color: #333333;">For more information, please visit our website: </span><span lang="EN-US" style="background-color: #fefdfa; color: #333333;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="background-color: #fefdfa; color: #333333;"><a href="http://www.semiconductorwafers.net/" style="color: #7d181e; text-decoration-line: none;">www.semiconductorwafers.net</a>,</span><br style="background-color: #fefdfa; color: #333333;" /><span style="background-color: #fefdfa; color: #333333;">send us email at </span><a href="mailto:sales@powerwaywafer.com" style="background-color: #fefdfa; color: #7d181e; text-decoration-line: none;">sales@powerwaywafer.com</a><span style="background-color: #fefdfa; color: #333333;"> and </span><a href="mailto:powerwaymaterial@gmail.com" style="background-color: #fefdfa; color: #7d181e; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-43944815343341933522019-12-11T19:41:00.000-08:002019-12-11T19:41:02.238-08:00Interface characteristics and electrical transport of Ge/Si heterojunction fabricated by low-temperature wafer bonding<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #333333;">We report a promising method for oxide-layer-free germanium (<b>Ge</b>)/silicon (Si) wafer bonding based on an amorphous Ge (a-Ge) intermediate layer between Si and Ge wafers. The effect of the exposure time (</span><i style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">t</i><span style="color: #333333;"> </span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">e</span><span style="color: #333333;">), during which the a-Ge is exposed to the air after sputtering and being taken out of the chamber on the bubble density at the bonded interface, is identified and a near-bubble-free Ge/Si bonded interface is achieved for the </span><i style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">t</i><span style="color: #333333;"> </span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">e</span><span style="color: #333333;"> of 3 s. The crystallization of a-Ge at Ge/Si bonded interface starts from a-Ge/Ge interface and it fully turns to be <b>single-crystal</b> Ge after post-annealing. The oxide layer at a-Ge/a-Ge bonded interface formed by the interface hydrophilic reaction disappears due to the atom redistribution triggered by the crystallization of a-Ge. As expected, the performance of the Ge/Si heterojunction diode is significantly improved by this oxide-layer-free Ge/Si bonded interface. A low dark current of 1.6 </span><i style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">µ</i><span style="color: #333333;">A, high on/off current ratio of 3.4 </span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; font-weight: 700; line-height: inherit; margin: 0px; padding: 0px; vertical-align: baseline;">×</span><span style="color: #333333;"> 10</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">5</span><span style="color: #333333;">, and low ideality factor of 1.02 (150 K) is achieved at −0.5 V for the bonded Ge/Si diode. Finally, the carrier transport mechanisms at Ge/Si bonded interface annealed at different temperatures are also clearly clarified.</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><span style="background-color: #fefdfa; color: #333333;">Source:IOPscience</span><br style="color: #333333;" /><span style="background-color: #fefdfa; color: #333333;">For more information, please visit our website: </span><span lang="EN-US" style="color: #333333;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="color: #333333;"><a href="http://www.semiconductorwafers.net/" style="color: #7d181e; text-decoration-line: none;">www.semiconductorwafers.net</a>,</span><br style="color: #333333;" /><span style="background-color: #fefdfa; color: #333333;">send us email at </span><a href="mailto:sales@powerwaywafer.com" style="color: #7d181e; text-decoration-line: none;">sales@powerwaywafer.com</a><span style="background-color: #fefdfa; color: #333333;"> and </span><a href="mailto:powerwaymaterial@gmail.com" style="color: #7d181e; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-12611125156878720482019-12-04T18:46:00.003-08:002019-12-04T18:46:41.930-08:00300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut™ Technology<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #333333;">We have fabricated 300 mm Si</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.3</span><span style="color: #333333;">Ge</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.7</span><span style="color: #333333;">-On-Insulator substrates with the SmartCut</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">TM</span><span style="color: #333333;"> approach. The donor wafers consisted in polished, 5 µm thick Si</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.3</span><span style="color: #333333;">Ge</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.7</span><span style="color: #333333;"> Strain-Relaxed Buffers (SRBs) on top of Si(001) substrates. The following stacks were deposited on top of those SRBs: (low<b> Ge</b> content SiGe / Si</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.3</span><span style="color: #333333;">Ge</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.7</span><span style="color: #333333;">) bilayers and (low Ge content SiGe / Si</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.3</span><span style="color: #333333;">Ge</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.7</span><span style="color: #333333;"> / low Ge content SiGe / Si</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.3</span><span style="color: #333333;">Ge</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.7</span><span style="color: #333333;">) multilayers. The thin, low Ge content SiGe layers were used as etch stops during the fabrication of the SiGeOI <b>wafers</b> and (in the second case) for the re-use of the expensive SRBs. A slight surface resurgence of the surface cross-hatch occurred as the deposited thicknesses became higher. The Ge content in the epitaxial layers was otherwise closely matched to that in the SRBs (70% instead of 68%) and some O peaks present at the Si</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.3</span><span style="color: #333333;">Ge</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.7</span><span style="color: #333333;"> / low Ge content SiGe interfaces. After H</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">+</span><span style="color: #333333;"> ion implantation, bonding and splitting, a SC1 solution was used to etch the Si</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.3</span><span style="color: #333333;">Ge</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.7</span><span style="color: #333333;"> layers and stop on the low Ge content SiGe layers. Meanwhile, TMAH was used in order to etch the low Ge content SiGe layers and stop on the Si</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.3</span><span style="color: #333333;">Ge</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.7</span><span style="color: #333333;"> layers. We obtained in the end 57 nm thick, flat Si</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.3</span><span style="color: #333333;">Ge</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">0.7</span><span style="color: #333333;"> layers (7.4 nm range) on top of the buried oxide (root mean square roughness: 0.3 nm only).</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><span style="background-color: #fefdfa; color: #333333;">Source:IOPscience<br />For more information, please visit our website: <span lang="EN-US"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US"><a href="http://www.semiconductorwafers.net/" style="color: #7d181e; text-decoration-line: none;">www.semiconductorwafers.net</a>,</span><br />send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #7d181e; text-decoration-line: none;">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #7d181e; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-61210654708179169452019-11-27T18:50:00.006-08:002019-11-27T18:50:51.347-08:00Evaluation of four inch diameter VGF-Ge substrates used for manufacturing multi-junction solar cell*<span style="font-family: Arial, Helvetica, sans-serif;"><span style="color: #333333;">Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, <b>etch pit density</b> (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">2</span><span style="color: #333333;">O</span><span style="border: 0px; color: #333333; font-stretch: inherit; font-variant-east-asian: inherit; font-variant-numeric: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; top: 0.5ex; vertical-align: baseline;">3</span><span style="color: #333333;"> encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, <b>lattice parameter</b>, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are <b>in contrast to</b> a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters.]</span></span><br />
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<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><span style="background-color: #fefdfa; color: #333333;">Source:IOPscience</span><br style="background-color: #fefdfa; color: #333333;" /><span style="background-color: #fefdfa; color: #333333;">For more information, please visit our website: </span><span lang="EN-US" style="background-color: #fefdfa; color: #333333;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="background-color: #fefdfa;"><a href="http://www.semiconductorwafers.net/" style="color: #7d181e; text-decoration-line: none;">www.semiconductorwafers.net</a>,</span><br style="background-color: #fefdfa; color: #333333;" /><span style="background-color: #fefdfa; color: #333333;">send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #7d181e; text-decoration-line: none;">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #7d181e; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-70306294323025252852019-11-19T23:43:00.004-08:002019-11-19T23:44:23.366-08:00Bubble evolution mechanism and stress-induced crystallization in low-temperature silicon wafer bonding based on a thin intermediate amorphous Ge layer<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;">The dependence of the morphology and crystallinity of an amorphous Ge (a-Ge) interlayer between two Si wafers on the annealing temperature is identified to understand the bubble evolution mechanism. The effect of a-Ge layer thickness on the bubble density and size at different annealing temperatures is also clearly clarified. It suggests that the bubble density is significantly affected by the <b>crystallinity</b> and thickness of the a-Ge layer. With the increase of the crystallinity and thickness of the a-Ge layer, the bubble density decreases. It is important that a near-bubble-free Ge interface, which is also an oxide-free interface, is achieved when the bonded Si wafers (a-<b>Ge</b> <b>layer thickness</b> ≥ 20 nm) are annealed at 400 °C. Furthermore, the crystallization temperature of the a-Ge between the bonded Si <b>wafers</b> is lower than that on a Si substrate alone and the Ge grains firstly form at the Ge/Ge bonded interface, rather than the Ge/Si interface. We believe that the stress-induced crystallization of a-Ge film and the intermixing of Ge atoms at the Ge/Ge interface can be responsible for this feature.</span></span><br />
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<span style="background-color: #fefdfa; color: #333333; font-family: "arial" , "helvetica" , sans-serif; font-size: 13px;">Source:IOPscience</span><br />
<span style="background-color: #fefdfa; color: #333333; font-family: arial, helvetica, sans-serif; font-size: 13px;">For more information, please visit our website: </span><span lang="EN-US" style="background-color: #fefdfa; color: #333333; font-family: arial, helvetica, sans-serif; font-size: 13px;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="background-color: #fefdfa; color: black; font-family: arial, helvetica, sans-serif; font-size: 13px;"><a href="http://www.semiconductorwafers.net/" style="color: #7d181e; text-decoration-line: none;">www.semiconductorwafers.net</a>,</span><br />
<span style="background-color: #fefdfa; color: #333333; font-family: "arial" , "helvetica" , sans-serif; font-size: 13px;">send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #7d181e; text-decoration-line: none;">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #7d181e; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-43650496121413061832019-11-11T18:24:00.002-08:002019-11-19T23:44:43.883-08:00Thin film germanium on silicon created via ion implantation and oxide trapping<span style="font-family: "arial" , "helvetica" , sans-serif;">We present a novel process for integrating <b>germanium </b>with silicon-on-insulator (SOI) wafers. Germanium is implanted into SOI which is then oxidized, trapping the germanium between the two oxide layers (the grown oxide and the buried oxide). With careful control of the implantation and oxidation conditions this process creates a <b>thin layer </b>(current experiments indicate up to 20-30nm) of almost pure germanium. The layer can be used potentially for fabrication of integrated photo-detectors sensitive to infrared wavelengths, or may serve as a seed for further germanium growth. Results are presented from <b>electron microscopy </b>and Rutherford back-scattering analysis, as well as preliminary modelling using an analytical description of the process.</span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><br /></span>
<span style="background-color: #fefdfa; color: #333333; font-family: "arial" , "helvetica" , sans-serif; font-size: 13px;">Source:IOPscience</span><br />
<span style="background-color: #fefdfa; color: #333333; font-family: arial, helvetica, sans-serif; font-size: 13px;">For more information, please visit our website: </span><span lang="EN-US" style="background-color: #fefdfa; color: #333333; font-family: arial, helvetica, sans-serif; font-size: 13px;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="background-color: #fefdfa; color: black; font-family: arial, helvetica, sans-serif; font-size: 13px;"><a href="http://www.semiconductorwafers.net/" style="color: #7d181e; text-decoration-line: none;">www.semiconductorwafers.net</a>,</span><br />
<span style="background-color: #fefdfa; color: #333333; font-family: "arial" , "helvetica" , sans-serif; font-size: 13px;">send us email at <a href="mailto:sales@powerwaywafer.com" style="color: #7d181e; text-decoration-line: none;">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com" style="color: #7d181e; text-decoration-line: none;">powerwaymaterial@gmail.com</a></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-19837801163379381512019-11-06T18:40:00.002-08:002019-11-19T23:44:54.682-08:00Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-offWe have developed a <b>wafer</b>-scale layer-transfer technique for transferring GaAs and <b>Ge</b> onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by <b>X-ray diffraction</b> (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.<br />
<br />
<span style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;">Source:IOPscience</span><br />
<span style="float: none; font-family: Arial, Helvetica, sans-serif; font-size: x-small;">For more information, please visit our website: </span><span lang="EN-US" style="font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; mso-wrap-style: square; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="color: black; font-family: Arial, Helvetica, sans-serif; font-size: x-small;"><a href="http://www.semiconductorwafers.net/">www.semiconductorwafers.net</a>,</span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none; font-family: Arial, Helvetica, sans-serif; font-size: x-small;">send us email at <a href="mailto:sales@powerwaywafer.com">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com">powerwaymaterial@gmail.com</a></span></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-41690378183672566692019-10-29T00:26:00.000-07:002019-11-06T18:41:47.733-08:00Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="color: #333333;">Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of <b>semiconductor</b> nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-Cut</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">TM</span><span style="color: #333333;"> technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-Cut</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">TM</span><span style="color: #333333;"> is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged <b>Ge wafer</b> because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-Cut</span><span style="border: 0px; bottom: 1ex; color: #333333; font-stretch: inherit; height: 0px; line-height: 1; margin: 0px; padding: 0px; position: relative; vertical-align: baseline;">TM</span><span style="color: #333333;"> process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.</span></span><br />
<span style="color: #333333;"><span style="font-family: "arial" , "helvetica" , sans-serif;"><br /></span></span>
<span style="font-family: "arial" , "helvetica" , sans-serif;">Source:IOPscience</span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><br /></span>
<div class="MsoNormal">
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none;">For more information, please visit our website: </span><span lang="EN-US" style="mso-no-proof: yes;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; mso-wrap-style: square; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="color: black;"><a href="http://www.semiconductorwafers.net/">www.semiconductorwafers.net</a>,</span></span></div>
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none; font-family: "arial" , "helvetica" , sans-serif;">send us email at <a href="mailto:sales@powerwaywafer.com">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com">powerwaymaterial@gmail.com</a></span></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-70257470255786968112019-08-21T23:36:00.004-07:002019-08-21T23:36:35.366-07:00Determination of the free carrier concentration in atomic-layer doped germanium thin films by infrared spectroscopy<div class="MsoNormal">
<span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">Novel silicon photonics applications
requiring heavy n-type doping have recently driven a great deal of interest
towards the phosphorous doping of germanium. In this work we report on infrared
reflectance spectroscopy measurements of the electron density in heavily <b>n-type
doped germanium layers</b> obtained by stacking multiple phosphorous δ-layers.
Here, we demonstrate that the conventional Drude model of the electrodynamic
response of free carriers in metals can be adapted to describe heavily doped
semiconductor thin films. Consequently, the effect of the electron density on
the plasma frequency, scattering rate and complex permittivity can be
investigated.<o:p></o:p></span></div>
<br />
<br />
<span style="font-family: "arial" , "helvetica" , sans-serif;">Source:IOPscience</span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><br /></span>
<div class="MsoNormal">
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none;">For more information, please visit our website: </span><span lang="EN-US" style="mso-no-proof: yes;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; mso-wrap-style: square; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="color: black;"><a href="http://www.semiconductorwafers.net/">www.semiconductorwafers.net</a>,</span></span></div>
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none; font-family: "arial" , "helvetica" , sans-serif;">send us email at <a href="mailto:sales@powerwaywafer.com">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com">powerwaymaterial@gmail.com</a></span></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-75887025352406619192019-08-16T03:08:00.004-07:002019-08-16T03:08:32.084-07:00Heat capacity of germanium crystals with various isotopic composition<div class="MsoNormal">
<span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">The heat capacity of three pure (n, p</span><span style="font-family: 宋体; font-size: 12pt;">≤</span><span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">2</span><span style="font-family: 宋体; font-size: 12pt;">×</span><span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">1016
cm-3) <b>germanium crystals</b> with different isotopic compositions was measured in
the temperature range from 2.8 K to 100 K. These samples, one made of enriched
70Ge (95.6%), Ge of natural isotopic composition and n, p < 1014 cm-3, and
one of the largest possible isotopic mass variance 70/76Ge (43%/48%) with n,
p<1014 cm-3, show a change of the molar heat capacity (and corresponding
Debye temperature, θD) as expected from the average mass variation,
corresponding to </span><span style="font-family: 宋体; font-size: 12pt;">θ</span><span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">D</span><span style="font-family: 宋体; font-size: 12pt;">∝</span><span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">M-0.5 (M = molar mass) at low temperatures. The mass
effect is best visible around 21.5 K, at the minimum of the corresponding Debye
temperatures </span><span style="font-family: 宋体; font-size: 12pt;">θ</span><span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">D, and amounts to </span><span style="font-family: 宋体; font-size: 12pt;">Δθ</span><span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">D = 5.3 K for the difference between the Debye
temperatures of 70Ge and 70/76Ge. The specific heat capacity of the natural Ge
crystal agrees within 2% with the best data available in the literature taken
on much larger masses of Ge.<o:p></o:p></span></div>
<br />
<br />
<span style="font-family: "arial" , "helvetica" , sans-serif;">Source:IOPscience</span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><br /></span>
<div class="MsoNormal">
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none;">For more information, please visit our website: </span><span lang="EN-US" style="mso-no-proof: yes;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; mso-wrap-style: square; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="color: black;"><a href="http://www.semiconductorwafers.net/">www.semiconductorwafers.net</a>,</span></span></div>
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none; font-family: "arial" , "helvetica" , sans-serif;">send us email at <a href="mailto:sales@powerwaywafer.com">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com">powerwaymaterial@gmail.com</a></span></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-20209304575246569292019-08-09T01:12:00.004-07:002019-08-09T01:12:42.447-07:00Thin germanium–carbon layers deposited directly on silicon for metal–oxide–semiconductor devices<div class="MsoNormal">
<span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">We report the growth process and materials
characterization of <b>germanium–carbon alloys</b> (Ge1−xCx) deposited directly on <b>Si
(1 0 0) substrates</b> by ultra-high-vacuum chemical vapour deposition. The Ge1−xCx
films are characterized by transmission electron microscopy, etch-pit density,
x-ray diffraction, secondary ion mass spectrometry and electron energy loss
spectroscopy. The results show that the films exhibit low threading dislocation
densities despite significant strain relaxation. We also present evidence for
carbon segregation in the Ge1−xCx and interpret these results as a strain
relaxation mechanism.<o:p></o:p></span></div>
<br />
<br />
<span style="font-family: "arial" , "helvetica" , sans-serif;">Source:IOPscience</span><br />
<span style="font-family: "arial" , "helvetica" , sans-serif;"><br /></span>
<div class="MsoNormal">
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none;">For more information, please visit our website: </span><span lang="EN-US" style="mso-no-proof: yes;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; mso-wrap-style: square; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="color: black;"><a href="http://www.semiconductorwafers.net/">www.semiconductorwafers.net</a>,</span></span></div>
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none; font-family: "arial" , "helvetica" , sans-serif;">send us email at <a href="mailto:sales@powerwaywafer.com">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com">powerwaymaterial@gmail.com</a></span></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-57176820132208691332019-08-01T01:34:00.001-07:002019-08-01T01:34:39.321-07:00New concept of planar germanium MOSFET with stacked germanide layers at source/drain<div class="MsoNormal">
<span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">In this paper, we have proposed and simulated
one novel Schottky barrier germanium-based MOSFET structure. Herein, the
source/drain region of the device is consisted with two stacked layers of
germanide materials. Different barrier heights of the top and bottom contact
are hence formed with channel respectively. The top barrier height is designed
lower enough to enlarge drive current, and the bottom barrier height is higher
(nearly mid-gap) to diminish the leakage current. The working mechanism and the
performance of n- and <b>p-type devices</b> is studied. Comparisons between dual
barrier structure and single barrier structure are also carried out. The
results show that the characteristics have been significantly enhanced with the
proposed dual barrier structure. Besides, the devices' performance is nearly
insensitive to germanium thickness, which leads to the relax of the requirement
of <b>germanium-on-insulator</b> (GeOI) structures for leakage immunization.<o:p></o:p></span></div>
<br />
<br />
<br />
<span style="font-family: "arial" , "helvetica" , sans-serif;">Source:IOPscience</span><br />
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<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none;">For more information, please visit our website: </span><span lang="EN-US" style="mso-no-proof: yes;"><v:shapetype coordsize="21600,21600" filled="f" id="_x0000_t75" o:preferrelative="t" o:spt="75" path="m@4@5l@4@11@9@11@9@5xe" stroked="f"> <v:stroke joinstyle="miter"><v:formulas><v:f eqn="if lineDrawn pixelLineWidth 0"><v:f eqn="sum @0 1 0"><v:f eqn="sum 0 0 @1"><v:f eqn="prod @2 1 2"><v:f eqn="prod @3 21600 pixelWidth"><v:f eqn="prod @3 21600 pixelHeight"><v:f eqn="sum @0 0 1"><v:f eqn="prod @6 1 2"><v:f eqn="prod @7 21600 pixelWidth"><v:f eqn="sum @8 21600 0"><v:f eqn="prod @7 21600 pixelHeight"><v:f eqn="sum @10 21600 0"></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:f></v:formulas><v:path gradientshapeok="t" o:connecttype="rect" o:extrusionok="f"><o:lock aspectratio="t" v:ext="edit"></o:lock></v:path></v:stroke></v:shapetype><v:shape id="图片_x0020_1" o:spid="_x0000_i1025" style="height: 11.25pt; mso-wrap-style: square; visibility: visible; width: 15pt;" type="#_x0000_t75"><v:imagedata o:title="%W@GJ$ACOF(TYDYECOKVDYB" src="file:///C:\Users\ADMINI~1\AppData\Local\Temp\msohtmlclip1\01\clip_image001.png"></v:imagedata></v:shape></span><span lang="EN-US" style="color: black;"><a href="http://www.semiconductorwafers.net/">www.semiconductorwafers.net</a>,</span></span></div>
<span style="font-family: "arial" , "helvetica" , sans-serif;"><span style="float: none; font-family: "arial" , "helvetica" , sans-serif;">send us email at <a href="mailto:sales@powerwaywafer.com">sales@powerwaywafer.com</a> and <a href="mailto:powerwaymaterial@gmail.com">powerwaymaterial@gmail.com</a></span></span>powerway wafer_Powerway Wafer Co., Limitedhttp://www.blogger.com/profile/13259129040002814344noreply@blogger.com0tag:blogger.com,1999:blog-7711851176515940734.post-70379452082541311272019-07-23T20:36:00.001-07:002019-07-23T20:36:09.080-07:00Characteristics of Germanium-on-Insulators Fabricated by Wafer Bonding and Hydrogen-Induced Layer Splitting<div class="MsoNormal">
<span lang="EN-US" style="font-family: Arial, sans-serif; font-size: 12pt;">There is considerable interest in
<b>germanium-on-insulator</b> (GeOI) because of its advantages in terms of device
performance and compatibility with silicon processing. In this paper,
fabricating GeOI by hydrogen-induced layer splitting and wafer bonding is discussed.
Hydrogen in germanium exists in molecular form and is prone to outdiffusion,
resulting in a storage-time dependence of blistering. In contrast to the case
of silicon, little effect of substrate doping on blistering is observed in
germanium. Hydrogen implantation in germanium creates both {100}- and
{111}-type microcracks. These two types of platelets are located in the same
region for (111)-oriented wafers, but in different zones for (100) samples.
This variation in distribution explains the smoother splitting of (111)
surfaces than that of (100) surfaces. Hydrogen implantation also introduces a
significant concentration of charged vacancies, which affect dopant diffusion
in the transferred germanium film. Boron, with a negligible Fermi-level dependence,
shows an identical diffusion profile to that of bulk germanium. In contrast,
phosphorus diffusion is enhanced in the fabricated <b>GeOI layers</b>. These results
also shed light on the understanding of dopant diffusion mechanisms in
germanium.<o:p></o:p></span></div>
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<span style="font-family: "arial" , "helvetica" , sans-serif;">Source:IOPscience</span><br />
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