2017年11月16日星期四

New Germanium-Based Material Could Replace Silicon for Electronics

The old adage “what goes around comes around” is now being applied in electronics. Before silicon ruled the roost as the electronics material of choice, the first transistors were fashioned out of germanium.

Now researchers at Ohio State University (OSU) are bringing germanium back to electronics in a way that they believe could displace silicon. To achieve its new role the researchers have manipulated the germanium down into a one-atom-thick material that gives it a two-dimensional structure not unlike graphene, thereby joining a growing list of 2-D materials targeted for electronic applications.


The researchers say that electrons conduct through their germanium-based material ten times faster than through silicon and five times faster than in traditional germanium.

Joshua Goldberger, assistant professor of chemistry at Ohio State, was attracted to the material because of the more than half century that has gone into characterizing and developing electronics around germanium, such as germanium MOSFETs.

“Most people think of graphene as the electronic material of the future,” Goldberger said in a press release. “But silicon and germanium are still the materials of the present. Sixty years’ worth of brainpower has gone into developing techniques to make chips out of them. So we’ve been searching for unique forms of silicon and germanium with advantageous properties, to get the benefits of a new material but with less cost and using existing technology.”

It is not an altogether novel idea. Researchers have attempted before to produce a stable 2-D structure from germanium—dubbed germanane. But in research that was published in the journal ACS Nano (“Stability and Exfoliation of Germanane: A Germanium Graphane Analogue”), Goldberger and his colleagues are the first to demonstrate how to do it successfully.

Germanium in its natural state forms into multi-layered crystal structures, and all previous attempts to strip it down to a single-atom layer has resulted in an unstable material. The Ohio State researchers overcame this by first placing calcium atoms between each layer of the germanium in its natural multi-layered state. They then dissolved the calcium with water. When the chemical bonds between the calcium atoms and the germanium were unattached, the researchers filled the empty bonding sites with hydrogen. It was at this point that the researchers were able to peel away stable one-atom thick layers from the germanium to create germanane.
With its new hydrogen-enhanced chemical structure, germanane is more stable than silicon. Unlike silicon, germanane will not oxidize in the presence of air or water.
So germanane beats silicon in electron conductivity and is not susceptible to oxidation. It also beats graphene in electronic applications because it has an inherent band gap and has 60 years of characterization for the electronics industry behind it.
I suspect that we are going to see a rash of papers talking about germanane now. And it should be interesting to see which 2-D material makes it into electronic applications first.
Source:IEEE
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2017年10月30日星期一

Toward tinier transistors

Toward tinier transistors

Introducing an interlayer of hafnium oxide reduces electron leakage between layers of germanium and titanium oxide, which can improve power efficiency and reliability.

(Phys.org) —The foundation of many, many modern electronic devices – including computers, smart phones, and televisions – is the silicon transistor. However, the shrinking of consumer electronics is driving researchers to investigate materials that can yield thinner transistors. At NSLS, researchers have used x-rays to probe the electronic behavior of a germanium-based transistor structure, yielding important information that will guide future studies of how to make transistors smaller.


A transistor is essentially a switch that regulates the flow of current. When a certain  is applied across it, current flows; below that, current does not flow. One very common transistor consists of a very thin (nanometer-scale) layer of an  (typically , SiO2) between a  and a .
Germanium (Ge) is favored to replace silicon in part because  move much faster within it than in silicon (Si). But the bigger issue is the oxide layer: When SiO2 approaches a thickness of one nanometer, electrons start to "leak" through it (a result of the strange physics phenomenon of quantum mechanical tunneling), leading to excess  and poor reliability. Transistors that use SiO2 cannot keep up with consumer demand for sleeker, faster devices.
Recently, companies like Intel have been making their transistors using hafnium oxide (HfO2), which can be thinner and still perform well. It has a higher "dielectric constant" (abbreviated K), which is the value that determines the robustness of any oxide against leakage: the higher the value of K, the lower the leakage. However, even HfO2 gets leaky when it's too thin.
Researchers are investigating oxides with higher K values, which, when combined with germanium, could yield a transistor more suited to tomorrow's electronics. But the most promising candidate,  (TiO2), also leaked too much current when placed into test structures, or "heterojunctions," regardless of whether the structures contained Si or Ge.
That leak was the result of a too-small "band offset." This means that the TiO2 conduction bands were not adequately separated from the Si and Ge bands, allowing electrons to leak from the Si or Ge to the TiO2. A large band offset is essential when the layers are so thin, helping to keep electrons from moving between them. One research group (led by Christophe Detavernier at Ghent University in Belgium) has found a good solution: adding a thin intermediate "interlayer" to their heterojunctions before depositing the TiO2 layer. The interlayer has a more reasonable band offset. The NSLS study has used this development as a jumping-off point.

"This way, you get the best of both: the good band offset from the interlayer and the high dielectric constant of titanium oxide," said NSLS scientist Abdul Rumaiz, the study's lead author. "However, with the scaling of devices to smaller sizes, the interlayer thickness needs to be less than one nanometer. Thus it is very crucial to understand the band offsets at such reduced dimensions."
Rumaiz and colleagues from the National Institute of Standards and Technology (NIST), Ghent University, Quaid-i-Azam University (Pakistan), and the University of Delaware studied how interlayer thickness affected band offsets. Using x-rays at beamline X24A, which is run by NIST, they investigated germanium-based transistor structures containing TiO2 and a hafnium oxide (HfO2) interlayer. This work and future studies will be important in determining how thin the layers can be while still yielding a highly performing transistor.
The team created six samples with different interlayer thicknesses, from 0.4 nanometers (nm) to 3 nm, and a fixed TiO2 thickness of 2 nm. They studied the structure with hard x-ray photoelectron spectroscopy, or HAXPES, a technique that measures the electrons a material emits when exposed to a beam of high-energy (hard) x-rays. These measurements can tell scientists about the bulk electronic properties of a material and also reveal information about the interfaces between materials.
They began with a germanium wafer, which formed a very thin "native oxide" layer after exposure to oxygen. On top of the native oxide, the team added the HfO2 and then the titanium oxide (TiO2) using a technique called atomic layer deposition.
The HAXPES analysis showed that as the thickness of the interlayer increased, band offsets also increased. It revealed several other electronic and structural details, too. For example, the germanium native oxide shifted to a higher oxidation state, meaning that it lost electrons and also increased in thickness. There was no evidence that the TiO2 layer mixed with the HfO2 layer, but there was evidence that the HfO2 layer mixed with the germanium oxide layer below it, forming Hf-Ge bonds. The results indicate that researchers need to be cautious about making assumptions about band offset.
Source:PHYS

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2017年10月23日星期一

Bubble evolution mechanism and stress-induced crystallization in low-temperature silicon wafer bonding based on a thin intermediate amorphous Ge layer

Abstract

The dependence of the morphology and crystallinity of an amorphous Ge (a-Ge) interlayer between two Si wafers on the annealing temperature is identified to understand the bubble evolution mechanism. The effect of a-Ge layer thickness on the bubble density and size at different annealing temperatures is also clearly clarified. It suggests that the bubble density is significantly affected by the crystallinity and thickness of the a-Ge layer. With the increase of the crystallinity and thickness of the a-Ge layer, the bubble density decreases. It is important that a near-bubble-free Ge interface, which is also an oxide-free interface, is achieved when the bonded Si wafers (a-Ge layer thickness  ≥  20 nm) are annealed at 400 °C. Furthermore, the crystallization temperature of the a-Ge between the bonded Si wafers is lower than that on a Si substrate alone and the Ge grains firstly form at the Ge/Ge bonded interface, rather than the Ge/Si interface. We believe that the stress-induced crystallization of a-Ge film and the intermixing of Ge atoms at the Ge/Ge interface can be responsible for this feature.
Source:IOPscience
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2017年10月20日星期五

Imec demonstrates strained germanium finFETs at IEDM 2013

At this week's IEEE International Electron Devices Meeting (IEDM 2013), imec reported the first functional strained germanium (Ge) quantum-well channel pMOS FinFETs, fabricated with a Si Fin replacement process on 300mm Si wafers. The device shows a possible evolution of the FinFET/trigate architecture for 7nm and 5nm CMOS technologies

Since the 90nm technology, embedded SiGe source/drain has been a popular stressor method to produce strained Si that enhances pMOS devices. With diminishing  dimensions, the volume to implement stressors in the source and drain has also been severely scaled. Especially, with thin-body devices like FinFETs, the difficulty is even more pronounced. A possible relief would be to implement highly-strained material directly into the channel itself.

Imec's solution, growing compressively strained Ge-channels on relaxed SiGe buffer, has already proven to boost the channel mobility, and is also known for its excellent scalability potential. The use of a fin replacement process to fabricate the strained Ge channel device makes it especially attractive for co-integration with other devices on a common Silicon substrate. The reported strained Ge p-channel FinFETs on SiGe trench buffer achieved peak transconductance (gmSAT )values of 1.3mS/µm at VDS=-0.5V with good short channel control down to 60nm gate length. The transconductance to subthreshold slope ratio of the devices (gmSAT/SSSAT)is high compared to published relaxed Ge FinFET devices.

Future developments will focus on improving the device performance through P-doping in the SiGe, optimizing Si cap passivation thickness on the Ge, and improving the gate wrap of the channel. "Unlike published Ge FinFETs, this work demonstrates a Ge-SiGe heterostructure-based quantum-well device in a FinFET form, which not only provides strain benefits but also enhancesshort-channel control," remarked Nadine Collaert, program manager of the Ge/IIIV device R&D.

"Just recently, we reported the implementation of IIIV material into the device architecture using a fin replacement process," stated Aaron Thean, director of the logic R&D program at imec. "This new achievement, implementing Ge into the  through our fin replacement process, is another key ingredient to our menu of process possibilities for monolithic heterogeneous integration to extend CMOS and SOCs."

Source:PHYS

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2017年9月24日星期日

Lifetime measurements on Ge wafers for Ge/GaAs solar cells — chemical surface passivation

Abstract

A rather unknown application of Ge is the use of Ge wafers in Ge/GaAs solar cells which provide the electrical supply of telecommunication satellites. The Ge wafers are used not only as a substrate for the epitaxially grown GaAs-based layers but also as a photovoltaic absorber layer contributing to the photocurrent and thus to the total efficiency of the solar cell. For the latter function the minority carrier lifetime of the Ge wafers is of major importance. Since most minority carrier lifetime measurements on semiconductor wafers have been made on Si (in particular commercial instrumentation and surface passivation) it was necessary to explore this domain for Ge wafers. Two types of lifetime measurements were used in this study: Photoconductive decay measurements (PCD) with contacts on rectangular wafer pieces and contactless microwave detected PCD (μ-PCD) on complete wafers. In order to measure the bulk recombination lifetime, passivation of the Ge surface is necessary. In this paper the chemical passivation of the Ge wafer surface is studied.

Keywords

Lifetime measurements
Ge
Solar cells
Chemical surface passivation

Source:ScienceDirect

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2017年9月5日星期二

Enhancement of carrier mobility in thin Ge layer by Sn co-doping

Abstract

We present the development, optimization and fabrication of high carrier mobility materials based on GeOI wafers co-doped with Sn and P. The Ge thin films were fabricated using plasma-enhanced chemical vapour deposition followed by ion implantation and explosive solid phase epitaxy, which is induced by millisecond flash lamp annealing. The influence of the recrystallization mechanism and co-doping of Sn on the carrier distribution and carrier mobility both in n-type and p-type GeOI wafers is discussed in detail. This finding significantly contributes to the state-of-the-art of high carrier mobility-GeOI wafers since the results are comparable with GeOI commercial wafers fabricated by epitaxial layer transfer or SmartCut technology.

Source:IOPscience

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2017年8月13日星期日

Strain relaxation of Ge-implanted silicon wafers

Abstract

In this work, Ge has been introduced into silicon wafers by ion implantation method to acquire surface-layer tensile strain. It has been demonstrated that there are different strain states among Ge-implanted silicon wafers with different implantation conditions: (1) high dose of 7 × 1016 cm−2 at room temperature; (2) high dose of 7 × 1016 cm−2 at liquid nitrogen temperature; (3) low dose of 6 × 1014 cm−2 at room temperature. It is demonstrated that the Ge-graded profile and such structures as the half-loop dislocations and Ge-rich nanoclusters may correlate with the appearance of few defects and the preservation of the elastic tensile strain in the surface layer of the first set of samples. In the second and third sets of samples no noticeable strains do appear. The reason of this behaviour might be ascribed to a large number of defects penetrating outside the surface and the low fraction of Ge, respectively.

Keywords

Ge
Silicon
Ion implantation
Strain

Source:ScienceDirect

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2017年8月10日星期四

Evaluation of four inch diameter VGF-Ge substrates used for manufacturing multi-junction solar cell*

Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, etch pit density (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B2O3 encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, lattice parameter, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are in contrast to a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters.

Source:IOPscience

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2017年8月1日星期二

A review of thermal processing in the subsecond range: semiconductors and beyond

Abstract

Thermal processing in the subsecond range comprises modern, non-equilibrium annealing techniques which allow various material modifications at the surface without affecting the bulk. Flash lamp annealing (FLA) is one of the most diverse methods for short-time annealing with applications ranging from the classical field of semiconductor doping to the treatment of polymers and flexible substrates. It still continues to extend its use to other material classes and applications, and is becoming of interest for an increasing number of users. In this review we present a short, but comprehensive and consistent picture of the current state-of-the-art of FLA, sometimes also called pulsed light sintering. In the first part we take a closer look at the physical and technological background, namely the electrical and optical specifications of flash lamps, the resulting temperature profiles, and the corresponding implications for process-relevant parameters such as reproducibility and homogeneity. The second part briefly considers the various applications of FLA, starting with the classical task of defect minimization and ultra-shallow junction formation in Si, followed by further applications in Si technology, namely in the fields of hyperdoping, crystallization of thin amorphous films, and photovoltaics. Subsequent chapters cover the topics of doping and crystallization in Ge and silicon carbide, doping of III–V semiconductors, diluted magnetic semiconductors, III–V nanocluster synthesis in Si, annealing of transparent conductive oxides and high-k materials, nanoclusters in dielectric matrices, and the use of FLA for flexible substrates.
Source:IOPscience
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2017年7月26日星期三

Imec demonstrates 50GHz Ge waveguide electro-absorption modulator

Imec demonstrates 50GHz Ge waveguide electro-absorption modulator
At this week's OFC 2015, the largest global conference and exposition for optical communications, nanoelectronics research center imec, its associated lab at Ghent University (Intec), and Stanford University have demonstrated a compact germanium (Ge) waveguide electro-absorption modulator (EAM) with a modulation bandwidth beyond 50GHz. Combining state-of-the-art extinction ratio and low insertion loss with an ultra-low capacitance of just 10fF, the demonstrated EAM marks an important milestone for the realization of next-generation silicon integrated optical interconnects at 50Gb/s and beyond.

Future chip-level optical interconnects require integrated optical modulators with stringent requirements for modulation efficiency and bandwidth, as well as for footprint and thermal robustness. In the presented work, imec and its partners have improved the state-of-the-art for Ge EAMs on Si, realizing higher modulation speed, higher modulation efficiency and lower capacitance. This was obtained by fully leveraging the strong confinement of the optical and electrical fields in the Ge waveguides, as enabled in imec's 200mm Silicon Photonics platform. The EAM was implemented along with various Si waveguide devices, highly efficient grating couplers, various active Si devices, and high speed Ge photodetectors, paving the way to industrial adoption of optical transceivers based on this device.

"This achievement is a milestone for realizing  optical transceivers for datacom applications at 50Gb/s and beyond," stated Joris Van Campenhout, program director at imec. "We have developed a modulator that addresses the bandwidth and density requirements for future ."

Companies can benefit from imec's Silicon Photonics platform (iSiPP25G) through established standard cells, or by exploring the functionality of their own designs in Multi-Project Wafer (MPW) runs. The iSiPP25G technology is available via ICLink services and MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs.

2017年7月17日星期一

Imec demonstrates 50GHz Ge waveguide electro-absorption modulator

At this week's OFC 2015, the largest global conference and exposition for optical communications, nanoelectronics research center imec, its associated lab at Ghent University (Intec), and Stanford University have demonstrated a compact germanium (Ge) waveguide electro-absorption modulator (EAM) with a modulation bandwidth beyond 50GHz. Combining state-of-the-art extinction ratio and low insertion loss with an ultra-low capacitance of just 10fF, the demonstrated EAM marks an important milestone for the realization of next-generation silicon integrated optical interconnects at 50Gb/s and beyond.
Future chip-level optical interconnects require integrated optical modulators with stringent requirements for modulation efficiency and bandwidth, as well as for footprint and thermal robustness. In the presented work, imec and its partners have improved the state-of-the-art for Ge EAMs on Si, realizing higher modulation speed, higher modulation efficiency and lower capacitance. This was obtained by fully leveraging the strong confinement of the optical and electrical fields in the Ge waveguides, as enabled in imec's 200mm Silicon Photonics platform. The EAM was implemented along with various Si waveguide devices, highly efficient grating couplers, various active Si devices, and high speed Ge photodetectors, paving the way to industrial adoption of optical transceivers based on this device.
"This achievement is a milestone for realizing  optical transceivers for datacom applications at 50Gb/s and beyond," stated Joris Van Campenhout, program director at imec. "We have developed a modulator that addresses the bandwidth and density requirements for future ."
Companies can benefit from imec's Silicon Photonics platform (iSiPP25G) through established standard cells, or by exploring the functionality of their own designs in Multi-Project Wafer (MPW) runs. The iSiPP25G technology is available via ICLink services and MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs.

2017年7月9日星期日

Geiger mode theoretical study of a wafer-bonded Ge on Si single-photon avalanche photodiode

Abstract

The investigation of the single-photon properties of a wafer-bonded Ge/Si single-photon avalanche photodiode (SPAD) is theoretically conducted. We focus on the effect of the natural GeO2 layer (hydrophilic reaction) at the Ge/Si wafer-bonded interface on dark count characteristics and single-photon response. It is found that the wafer-bonded Ge/Si SPAD exhibits very low dark current at 250 K due to the absence of threading dislocation (TD) in the Ge layer. Owing to the increase of the unit-gain bias applied on the SPAD, the primary dark current (I DM) increases with the increase in GeO2thickness. Furthermore, the dependence of the linear-mode gain and 3 dB bandwidth (BW) for the dark count on GeO2 thickness is also presented. It is observed that the dark count probability of the Ge/Si SPAD significantly increases with the increase in GeO2 thickness due to the increase of the IDM and the reduction of the 3 dB BW. It is also found that with the increase in GeO2 thickness, the external quantum efficiency, which affects the single-photon detection efficiency (SPDE), drastically decreases because of the blocking effect of the GeO2 layer and the serious recombination at the wafer-bonded Ge/Si interface. The afterpulsing probability (AP) shows an abnormal behavior with GeO2 thickness. This results from the decrease in avalanche charge and increase in effective transit time.
Keywords:GeO2thickness,single-photon avalanche photodiode (SPAD),
Source:  Iopscience
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2017年7月7日星期五

Fabrication of high quality, thin Ge-on-insulator layers by direct wafer-bonding for nanostructured thermoelectric devices

Abstract

A simple means of fabricating thin Ge-on-insulator (GOI) layers with a strong bond at the Ge/SiO2interface through direct wafer-bonding is described. In this work, high quality Ge/SiO2 bonding was achieved under ambient air and at room temperature as a result of the extremely hydrophilic bonding surfaces obtained by chemical treatment prior to direct bonding. Based on the results of this work, the first-ever bonding mechanism between ammonium hydroxide treated Ge and SiO2/Si wafer surfaces is proposed. In addition, strain generated during post-annealing as a consequence of the significant thermal-expansion mismatch between Ge and SiO2 was gradually relieved by applying a multistep-cooling process. Structural characteristics of the thin GOI layer were analyzed by cross-sectional scanning electron microscopy, Raman spectroscopy, x-ray diffraction and transmission electron microscopy. It was determined that direct wafer-bonding followed by polishing could produce a GOI layer as thin as 156 nm, with sub-nm surface roughness.
Keywords:Ge-on-insulator (GOI) ,Ge/SiO2,
Source:  Iopscience
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2017年6月30日星期五

Synchrotron x-ray characterization of structural defects in epi-Ge/Pr2O3/Si(1 1 1) layer stacks

Abstract

Epi-Ge/Pr2O3/Si(1 1 1) layer structures were studied by synchrotron grazing incidence diffraction to analyse the structural perfection of the top epi-Ge and the oxide buffer layer independently. The dominating features for the epi-Ge layer are pronounced streaks of diffuse scattering in the lang1 1 1rangdirections that are caused by microtwins and stacking faults lying in the {1 1 1} glide planes 70.5° tilted to the wafer surface. It is confirmed that grains of type B orientation in the epi-Ge layer are located near the oxide–Ge interface only. The few nanometres thick Pr2O3 buffer layer shows similar streaks of diffuse scattering indicating a high concentration of structural defects in the tilted {1 1 1} planes. The relatively poor crystallographic quality of the oxide layer with an in-plane domain size of about 35 nm, a mosaicity of 0.7° and a strain variation of 0.8% is discussed as a possible reason for structural imperfections in the upper epi-Ge layer. Measurements on samples with different epi-Ge thicknesses show that the epi-Ge layer has no influence on the strain state of the Pr2O3 buffer layer.
Source:  Iopscience
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2017年6月27日星期二

Single layer of Ge quantum dots in HfO2 for floating gate memory capacitors

High performance trilayer memory capacitors with a floating gate of a single layer of Ge quantum dots (QDs) in HfO2 were fabricated using magnetron sputtering followed by rapid thermal annealing (RTA). The layer sequence of the capacitors is gate HfO 2/floating gate of single layer of Ge QDs in HfO2/tunnel HfO 2/p-Si wafers. Both Ge and HfO2 are nanostructured by RTA at moderate temperatures of 600–700 °C. By nanostructuring at 600 °C, the formation of a single layer of well separated Ge QDs with diameters of 2–3 nm at a density of 4–5 × 1015 m–2 is achieved in the floating gate (intermediate layer). The Ge QDs inside the intermediate layer are arranged in a single layer and are separated from each other by HfO2 nanocrystals (NCs) about 8 nm in diameter with a tetragonal/orthorhombic structure. The Ge QDs in the single layer are located at the crossing of the HfO2 NCs boundaries. In the intermediate layer, besides Ge QDs, a part of the Ge atoms is segregated by RTA at the HfO2 NCs boundaries, while another part of the Ge atoms is present inside the HfO2 lattice stabilizing the tetragonal/orthorhombic structure. The fabricated capacitors show a memory window of 3.8 ± 0.5 V and a capacitance–time characteristic with 14% capacitance decay in the first 3000–4000 s followed by a very slow capacitance decrease extrapolated to 50% after 10 years. This high performance is mainly due to the floating gate of a single layer of well separated Ge QDs in HfO2, distanced from the Si substrate by the tunnel oxide layer with a precise thickness.

Keywords: quantum dots (QDs);HfO2;RTA;nanocrystals (NCs);Ge QDs;

Source:iopscience


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