Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding
We propose the Ge CMOS photonics platform with Ge-on-Insulator (GOI) substrate on which Ge mid-infrared photonic devices and Ge CMOS transistors can be monolithically integrated. The GOI wafer for the Ge CMOS photonics was fabricated by combining wafer bonding and H ion cut technologies. We studied the effect of thermal annealing on the GOI substrate in terms of crystal quality, surface morphology and electrical property. From Raman spectrum, it was found that the crystal quality of the Ge layer was significantly recovered after a 550 °C annealing in N2 (or O2) ambient for 1 h. Meanwhile, the surface roughness of the GOI substrate remained very low even after the annealing process. As a result, the significant improvements on electrical properties of the GOI substrate were confirmed by Hall measurement results. The carrier density of a GOI Hall device decreases from 2.9×1016 to 8.9×1015 cm−3 and hole mobility increases from 925 to 2295 cm2/V s. These results strongly suggest the necessity of a proper thermal annealing on improving the GOI qualities.
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