Compressively strained germanium-on-insulator (c-GeOI) substrates with a definitely reduced defect density are expected to yield superior hole mobilities together with low off-state currents in p-type metal oxide semiconductor field effect transistors (MOSFETs). In order to fabricate c-GeOI wafers, we started with double-side polished Si(0 0 1) substrates and grew, by reduced pressure-chemical vapour deposition, Si0.15Ge0.85 virtual substrates (VS) on the front side. The wafer curvature was compensated thanks to the deposition of a thick Ge layer on the backside. We then grew, after a chemical mechanical polishing, various thickness (37–148 nm) Ge layers. They stayed smooth (root-mean-square roughness <5 Å) and pseudomorphically strained on the VS underneath (perpendicular lattice parameter: 5.681 Å Leftrightarrow bulk Ge lattice parameter: 5.658 Å) up to a 74 nm thickness. These c-Ge layers were then bonded on oxidized Si substrates using the SmartCut™ process. The resulting c-GeOI substrates were of high crystalline quality, compressively strained and smooth. The threading dislocations density (8 × 105 cm−2 Leftrightarrow 1.7 × 105 cm−2 for the SiGe VS template used to strain the c-Ge layers) was indeed 20 times less than the one associated with conventional GeOI substrates obtained from thick Ge epilayers. Pseudo-MOSFET measurements were performed to quantify the hole mobility gain in those c-GeOI substrates. A +150% enhancement compared to conventional silicon-on-insulator substrates was evidenced, validating the interest of these stacks.
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