(Invited) Ge/III-V Heterostructures and Their Applications in Fabricating Engineered Substrates

Chip level integration of III-V devices with Si-CMOS platform requires the use of engineered substrates. Fabrication of engineered substrates utilizes technologies such as epitaxy, wafer bonding and layer transfer. We report on two aspects of III-V/IV materials integration developments that are on the path to enabling Ge-on-insulator (GeOI) and GaAs-on-insulator (GaAsOI) on Si substrates without the use of SmartcutTM technology. We report on the establishment of Ge/AlAs/GaAs and GaAs/Ge/GaAs epitaxial structures/sequences with low defect density and surface properties suitable for wafer bonding. The epitaxial structures have embedded layers that offer highly selective etch properties that facilitate lift-off onto Si substrates. We demonstrate the use of these novel Ge/III-V heterostructures to liftoff layers of Ge through an aqueous hydrogen fluoride (HF) based epitaxial lift-off (ELO) process, or layers of GaAs through a gas phased ELO process enabled by xenon difluoride (XeF2) selective etching of Ge.

Source:IOPscience

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