(Invited) Ge/III-V Heterostructures and Their Applications in Fabricating Engineered Substrates

Chip level integration of III-V devices with Si-CMOS platform requires the use of engineered substrates. Fabrication of engineered substrates utilizes technologies such as epitaxy, wafer bonding and layer transfer. We report on two aspects of III-V/IV materials integration developments that are on the path to enabling Ge-on-insulator (GeOI) and GaAs-on-insulator (GaAsOI) on Si substrates without the use of SmartcutTM technology. We report on the establishment of Ge/AlAs/GaAs and GaAs/Ge/GaAs epitaxial structures/sequences with low defect density and surface properties suitable for wafer bonding. The epitaxial structures have embedded layers that offer highly selective etch properties that facilitate lift-off onto Si substrates. We demonstrate the use of these novel Ge/III-V heterostructures to liftoff layers of Ge through an aqueous hydrogen fluoride (HF) based epitaxial lift-off (ELO) process, or layers of GaAs through a gas phased ELO process enabled by xenon difluoride (XeF2) selective etching of Ge.

Source:IOPscience

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Selective Epitaxial Growth of Germanium on Si Wafers with Shallow Trench Isolation: An Approach for Ge Virtual Substrates

Ge selective epitaxial growth (SEG) in shallow trench isolated windows is of great interest in advanced devices due to the good lateral electrical isolation of shallow trenches and the possibility of integrating Ge on Si wafers. However, the high density of threading dislocations in strain-relaxed Ge layers and facet formation are two major concerns in Ge SEG. In this work, we have obtained facet-free growth of Ge in shallow trench isolated Si windows with a threading dislocation density (TDD) of 4.2×108 cm-2. A mass transport model is developed to simulate the Ge faceting and the factors influencing the Ge deposition selectivity are studied.

Source:IOPscience

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Double intermediate bonding layers for the fabrication of high-quality silicon-on-insulator-based exfoliated Ge film with excellent high-temperature characteristics

We investigate the high-temperature characteristics of wafer-bonded silicon-on-insulator (SOI)-based Ge film with two different intermediate bonding layers. For an amorphous Ge (a-Ge) bonding layer, due to the crystallization of a-Ge, many gas bubbles appear at the bonded interface to form Ge pits on the SOI. When the wafer pairs are annealed at  ≥400 °C, new gas bubbles appear and merge, leading to cracking of the Ge film due to the fact that the new gas bubbles cannot be transferred sufficiently rapidly out of the bonded interface of two single-crystal materials. For an a-Ge/a-Si bonding layer, the porous a-Si can serve as a reservoir at the bonded interface to absorb the by-products. With increase in a-Si layer thickness, the gas bubble density decreases. New gas bubbles are not observed after annealing at 500 °C when a 30 nm thick a-Si layer is introduced. More importantly, the quality of the Ge film with an a-Ge/a-Si bonding layer significantly improves after post-annealing. This can be explained by the repair of the point defects and restraining of the nucleation of threading dislocations by a-Si (no crystal orientation). This work presents high-quality heterogeneous hybrid integration of photoelectric materials by wafer bonding, which may give guidance for the low-temperature integration of Ge/Si, GeSn/Si and III–V/Si.

Source:IOPscience

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Coplanar Integration of Lattice-Mismatched Semiconductors with Silicon by Wafer Bonding Ge / Si1 − x Ge x / Si Virtual Substrates

We have demonstrated a general process which could be used for the integration of lattice-mismatched semiconductors onto large, Si-sized wafers by wafer bonding  virtual substrates. The challenges for implementing this procedure for large diameter Ge-on-insulator (GOI) have been identified and solved, resulting in the transfer of epitaxial  to a Si wafer. We found that planarization of Ge virtual substrates was a key limiting factor in the transfer process. To circumvent this problem, an oxide layer was first deposited on the Ge film before planarization using a standard oxide chemical mechanical planarization process. The GOI structure was created using -induced layer exfoliation (Smartcut™) and a buried  etch-stop layer, which was used to subsequently remove the surface damage with a hydrogen peroxide selective etch. After selective etching, the crosshatched surface morphology of the original virtual substrate was preserved with roughness of <15 nm rms as measured on a  scale and a  scale roughness of  Using an etch-stop layer, the transferred device layer thickness is defined epitaxially allowing for future fabrication of ultrathin GOI as well as III-V films directly on large-diameter Si wafers. © 2004 The Electrochemical Society. All rights reserved.

Source:IOPscience

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Two-dimensional arrays of nanometre scale holes and nano-V-grooves in oxidized Si wafers for the selective growth of Ge dots or Ge/Si hetero-nanocrystals

Two-dimensional (2D) arrays of nanometre scale holes were opened in thin SiO2 layers on silicon by electron beam lithography and chemical etching. Oxidized silicon wafers with a 5 nm thick SiO2 layer on top were used in this respect. Pattern transfer involved either only removal of SiO2 or a two-step process of oxide removal and anisotropic silicon chemical etching to form nanometre scale silicon V-grooves. The size of the holes in the photoresist layer varied in the range 40–80 nm, depending on the exposure dose used. The smallest holes in the oxide were about 50 nm in diameter, while in V-grooves the smallest width was  nm. 2D arrays of Ge dots or Ge/Si hetero-nanocrystals were selectively grown on these patterned silicon wafers. In small windows only one Ge island per hole was nucleated.

Source:IOPscience

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High Quality Ge Virtual Substrates on Si Wafers with Standard STI Patterning

Further improving complementary metal oxide semiconductor performance beyond the 22 nm generation likely requires the use of high mobility channel materials, such as Ge for p-type metal oxide semiconductor (pMOS) and III/V for n-type metal oxide semiconductor devices. The complementary integration of both materials on Si substrates can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates using Si wafers with standard shallow trench isolation (STI). This reduces the fabrication cost of these virtual substrates as the complicated isolation scheme in blanket Ge can be omitted. The low topography enables integration of ultrathin high- gate dielectrics. The fabrication schemes are also compatible with uniaxial stress techniques. Both modules include an annealing step at  to reduce the threading dislocation densities down to  and , respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter are illustrated by preliminary results of selective epitaxial InGaAs growth on virtual Ge substrates.

Source:IOPscience

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Lateral Gemanium Growth for Local GeOI Fabrication

High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. By plan view TEM it is shown, that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] or equivalent direction. The resulting Ge grown toward [010] direction contains no dislocations. A root mean square of roughness of ~0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.

Source:IOPscience

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