2020年1月20日星期一

Analysis of Trace Levels of Ge Transferred to Si Wafer Surfaces during SiGe Wafer Processing

Effects of trace levels of Ge transferred to Si surfaces during thermal processing of SiGe wafers are presented here. Si wafers were coprocessed in an oxidation furnace with SiGe relaxed graded buffer layers grown on Si. Total X-ray fluorescence measurements on Si wafers showed Ge concentrations in varying degrees depending on oxidation temperature, time, and the number of coprocessed SiGe wafers. The Ge concentration level increases with increase of oxidation time, temperature, and SiGe wafer quantity. It was also observed that the furnace shows "memory" of the process during subsequent process runs. A chlorine-based purge of the oxidation tube after processing SiGe wafers helps reduce the Ge concentration remarkably. Metal oxide semiconductor capacitance and gate leakage characterization were used to evaluate the effects of transferred Ge on the gate oxide. The interface state density is marginally higher on Si wafers with transferred Ge. © 2003 The Electrochemical Society. All rights reserved.

Source:IOPscience

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2020年1月13日星期一

Room Temperature Bonding of Wafers Using Si and Ge Films with Extremely Low Electrical Conductivity

The technical potential of room temperature bonding of wafers in vacuum using amorphous Si (a-Si) and Ge (a-Ge) films was studied. Transmission electron microscopy images revealed no interface corresponding to the original films surfaces for bonded a–Ge–a–Ge films. Analyses of film structure and the surface free energy at the bonded interface revealed higher bonding potential at the connected a–Ge–a–Ge interface than that of a–Si films. The electrical resistivity of a-Ge films is 0.62 Ωm, which is lower than that of a-Si film (4.7 Ωm), but 7–8 order higher than that of representative material films used for bonding in vacuum. Our results indicate that room temperature bonding using a–Ge films is useful to bond wafers without any marked influence on the electrical properties of devices on wafer surfaces caused by the electrical conductivity of films used for bonding.

Source:IOPscience

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2019年12月25日星期三

(Invited) Significant Enhancement of High-Ns Electron Mobility in Ge n-MOSFETs with Atomically Flat Ge/GeO2 Interface

The rapid degradation of high-Ns electron mobility in Ge n-MOSFETs is still one of the greatest concerns in Ge CMOS technology. Although there are many possible origins so far considered, the degradation mechanism is still unclear in spite of its importance. In this work, we clarify wafer-related origins for electron mobility degradation in Ge n-MOSFETs. High-Ns electron mobility is dramatically improved thanks to (i) atomically flat Ge surface formation, followed by (ii) layer-by-layer oxidation. (iii) Oxygen-related neutral impurities in Ge substrates could be another origin of the mobility reduction on Ge wafers. By successfully eliminating these scattering sources in Ge n-MOSFETs, we demonstrate intrinsically high electron mobility in a wide range of Ns.

Source:IOPscience

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2019年12月11日星期三

Interface characteristics and electrical transport of Ge/Si heterojunction fabricated by low-temperature wafer bonding

We report a promising method for oxide-layer-free germanium (Ge)/silicon (Si) wafer bonding based on an amorphous Ge (a-Ge) intermediate layer between Si and Ge wafers. The effect of the exposure time (t e), during which the a-Ge is exposed to the air after sputtering and being taken out of the chamber on the bubble density at the bonded interface, is identified and a near-bubble-free Ge/Si bonded interface is achieved for the t e of 3 s. The crystallization of a-Ge at Ge/Si bonded interface starts from a-Ge/Ge interface and it fully turns to be single-crystal Ge after post-annealing. The oxide layer at a-Ge/a-Ge bonded interface formed by the interface hydrophilic reaction disappears due to the atom redistribution triggered by the crystallization of a-Ge. As expected, the performance of the Ge/Si heterojunction diode is significantly improved by this oxide-layer-free Ge/Si bonded interface. A low dark current of 1.6 µA, high on/off current ratio of 3.4  ×  105, and low ideality factor of 1.02 (150 K) is achieved at  −0.5 V for the bonded Ge/Si diode. Finally, the carrier transport mechanisms at Ge/Si bonded interface annealed at different temperatures are also clearly clarified.

Source:IOPscience
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2019年12月4日星期三

300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut™ Technology

We have fabricated 300 mm Si0.3Ge0.7-On-Insulator substrates with the SmartCutTM approach. The donor wafers consisted in polished, 5 µm thick Si0.3Ge0.7 Strain-Relaxed Buffers (SRBs) on top of Si(001) substrates. The following stacks were deposited on top of those SRBs: (low Ge content SiGe / Si0.3Ge0.7) bilayers and (low Ge content SiGe / Si0.3Ge0.7 / low Ge content SiGe / Si0.3Ge0.7) multilayers. The thin, low Ge content SiGe layers were used as etch stops during the fabrication of the SiGeOI wafers and (in the second case) for the re-use of the expensive SRBs. A slight surface resurgence of the surface cross-hatch occurred as the deposited thicknesses became higher. The Ge content in the epitaxial layers was otherwise closely matched to that in the SRBs (70% instead of 68%) and some O peaks present at the Si0.3Ge0.7 / low Ge content SiGe interfaces. After H+ ion implantation, bonding and splitting, a SC1 solution was used to etch the Si0.3Ge0.7 layers and stop on the low Ge content SiGe layers. Meanwhile, TMAH was used in order to etch the low Ge content SiGe layers and stop on the Si0.3Ge0.7 layers. We obtained in the end 57 nm thick, flat Si0.3Ge0.7 layers (7.4 nm range) on top of the buried oxide (root mean square roughness: 0.3 nm only).

Source:IOPscience
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2019年11月27日星期三

Evaluation of four inch diameter VGF-Ge substrates used for manufacturing multi-junction solar cell*

Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, etch pit density (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B2O3 encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, lattice parameter, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are in contrast to a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters.]

Source:IOPscience
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2019年11月19日星期二

Bubble evolution mechanism and stress-induced crystallization in low-temperature silicon wafer bonding based on a thin intermediate amorphous Ge layer

The dependence of the morphology and crystallinity of an amorphous Ge (a-Ge) interlayer between two Si wafers on the annealing temperature is identified to understand the bubble evolution mechanism. The effect of a-Ge layer thickness on the bubble density and size at different annealing temperatures is also clearly clarified. It suggests that the bubble density is significantly affected by the crystallinity and thickness of the a-Ge layer. With the increase of the crystallinity and thickness of the a-Ge layer, the bubble density decreases. It is important that a near-bubble-free Ge interface, which is also an oxide-free interface, is achieved when the bonded Si wafers (a-Ge layer thickness  ≥  20 nm) are annealed at 400 °C. Furthermore, the crystallization temperature of the a-Ge between the bonded Si wafers is lower than that on a Si substrate alone and the Ge grains firstly form at the Ge/Ge bonded interface, rather than the Ge/Si interface. We believe that the stress-induced crystallization of a-Ge film and the intermixing of Ge atoms at the Ge/Ge interface can be responsible for this feature.

Source:IOPscience
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