2018年3月13日星期二

Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

Source:IOPscience

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2018年3月5日星期一

Chemical vapour etching of Si, SiGe and Ge with HCl; applications to the formation of thin relaxed SiGe buffers and to the revelation of threading dislocations

We have studied the etching of silicon, SiGe and germanium layers with gaseous HCl in reduced pressure-chemical vapour deposition (RP-CVD). We have observed the occurrence of two etch regimes depending on the etching temperature. The first regime takes place at high temperatures and is characterized by low activation energies (~7 kcal mol−1), this whatever the germanium content of the etched layer. The other regime occurs at low temperatures and has associated high activation energies (which strongly depend upon the germanium concentration of the etched layer: 86 kcal mol−1 for pure Si versus 28 kcal mol−1 for pure Ge). Modifying the HCl partial pressure has different effects depending on the regime. In the high temperature regime, increasing the HCl partial pressure will almost quadratically increase the etch rate (ER ∝ PHCl1.76), this both for Si and Si0.67Ge0.33. Meanwhile, the dependence is sub-linear in the low temperature regime (Si ER ∝ PHCl0.53 and Si0.67Ge0.33 ER ∝ PHCl0.82). The temperature where the regime shifts from one to the other decreases when the Ge concentration increases. To illustrate the added value of the chemical vapour etching, we have demonstrated two possible applications. The first one is the realization of SiGe thin strain relaxed buffers (TSRBs) in the active areas of shallow trench isolation (STI) patterned wafers after etching away the silicon with HCl. We have observed the occurrence of some etching loading effects when moving from a blanket to a patterned wafer. The SiGe TSRBs exhibit some good structural properties (rms roughness of 0.12 nm, no defects observed in cross-sectional transmission electron microscopy). However, they are not fully relaxed and facets are present at the STI/epitaxial stack boundary, signifying they are still not mature enough to be integrated in a metal oxide semiconductor technology. Another possible application is to decorate through some in situ HCl etching the dislocations threading through SiGe relaxed thick layers, with some significant advantages over commonly used wet etching solutions such as the Secco and the Schimmel ones.

Source:IOPscience

For more information, please visit our website: http://www.semiconductorwafers.net,
send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com