2020年2月25日星期二

Lateral Gemanium Growth for Local GeOI Fabrication

High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. By plan view TEM it is shown, that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] or equivalent direction. The resulting Ge grown toward [010] direction contains no dislocations. A root mean square of roughness of ~0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.

Source:IOPscience

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2020年2月19日星期三

The Characteristics of Interface Microstructures in Germanium/SiO2 Low Temperature Wafer Bonding

Ge/SiO2 direct wafer bonding by O2-plasma pretreatment was investigated. The bonding interfaces of Ge/SiO2 low temperature direct wafer bonding were characterized by transmission electron microscopy. The perfectly atomic level Ge/SiO2 bonding was achieved after a 1500C annealing for 60 hours. The excessive O2-plasma exposure resulted in micro-crack formation close to the bonding interface in Ge. A model involved micro-crack formed in Ge was proposed. Our experiments, for the first time, demonstrated that a perfectly seamless bonding of Ge/SiO2 by O2-plasma pretreatment depends not only on optimal O2-plasma pretreatment time but also on the manner of the raised annealing temperature to enhance the bonding strength. A slowly ramping rate heating is crucial to accomplish perfectly seamless Ge/SiO2 wafer bonding apart from an optimal O2-plasma exposure time chosen.

Source:IOPscience

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2020年2月12日星期三

(Invited) Device and Integration Technologies of III-V/Ge Channel CMOS

One of the ultimate CMOS structures can be the combination of III-V nMOSFETs and Ge pMOSFETs. In this presentation, we focus on the possible solutions for realizing CMOS integration of III-V and Ge MOSFETs. In order to realize the integration of III-V/Ge MOSFETs, the direct wafer bonding is a promising way. The gate stack formation is also a critical issue for III-V/Ge CMOS integration. We have employed Al2O3 gate insulators for both InGaAs and Ge MOSFETs. We have recently realized Al2O3/GeOx/Ge MOS gate stacks with low Dit and thin EOT by employing ALD Al2O3 and successive plasma oxidation. We consider that metal S/D scheme can be the best solution for III-V/Ge CMOS. We have implemented Ni-based metal S/D technologies for InGaAs and Ge MOSFETs. By employing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

Source:IOPscience


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send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com