Ge selective epitaxial growth (SEG) in shallow trench isolated windows is of great interest in advanced devices due to the good lateral electrical isolation of shallow trenches and the possibility of integrating Ge on Si wafers. However, the high density of threading dislocations in strain-relaxed Ge layers and facet formation are two major concerns in Ge SEG. In this work, we have obtained facet-free growth of Ge in shallow trench isolated Si windows with a threading dislocation density (TDD) of 4.2×108 cm-2. A mass transport model is developed to simulate the Ge faceting and the factors influencing the Ge deposition selectivity are studied.
Source:IOPscience
We investigate the high-temperature characteristics of wafer-bonded silicon-on-insulator (SOI)-based Ge film with two different intermediate bonding layers. For an amorphous Ge (a-Ge) bonding layer, due to the crystallization of a-Ge, many gas bubbles appear at the bonded interface to form Ge pits on the SOI. When the wafer pairs are annealed at ≥400 °C, new gas bubbles appear and merge, leading to cracking of the Ge film due to the fact that the new gas bubbles cannot be transferred sufficiently rapidly out of the bonded interface of two single-crystal materials. For an a-Ge/a-Si bonding layer, the porous a-Si can serve as a reservoir at the bonded interface to absorb the by-products. With increase in a-Si layer thickness, the gas bubble density decreases. New gas bubbles are not observed after annealing at 500 °C when a 30 nm thick a-Si layer is introduced. More importantly, the quality of the Ge film with an a-Ge/a-Si bonding layer significantly improves after post-annealing. This can be explained by the repair of the point defects and restraining of the nucleation of threading dislocations by a-Si (no crystal orientation). This work presents high-quality heterogeneous hybrid integration of photoelectric materials by wafer bonding, which may give guidance for the low-temperature integration of Ge/Si, GeSn/Si and III–V/Si.
Source:IOPscience
Two-dimensional (2D) arrays of nanometre scale holes were opened in thin SiO2 layers on silicon by electron beam lithography and chemical etching. Oxidized silicon wafers with a 5 nm thick SiO2 layer on top were used in this respect. Pattern transfer involved either only removal of SiO2 or a two-step process of oxide removal and anisotropic silicon chemical etching to form nanometre scale silicon V-grooves. The size of the holes in the photoresist layer varied in the range 40–80 nm, depending on the exposure dose used. The smallest holes in the oxide were about 50 nm in diameter, while in V-grooves the smallest width was nm. 2D arrays of Ge dots or Ge/Si hetero-nanocrystals were selectively grown on these patterned silicon wafers. In small windows only one Ge island per hole was nucleated.
Source:IOPscience