Chip level integration of III-V devices with Si-CMOS platform requires the use of engineered substrates. Fabrication of engineered substrates utilizes technologies such as epitaxy, wafer bonding and layer transfer. We report on two aspects of III-V/IV materials integration developments that are on the path to enabling Ge-on-insulator (GeOI) and GaAs-on-insulator (GaAsOI) on Si substrates without the use of SmartcutTM technology. We report on the establishment of Ge/AlAs/GaAs and GaAs/Ge/GaAs epitaxial structures/sequences with low defect density and surface properties suitable for wafer bonding. The epitaxial structures have embedded layers that offer highly selective etch properties that facilitate lift-off onto Si substrates. We demonstrate the use of these novel Ge/III-V heterostructures to liftoff layers of Ge through an aqueous hydrogen fluoride (HF) based epitaxial lift-off (ELO) process, or layers of GaAs through a gas phased ELO process enabled by xenon difluoride (XeF2) selective etching of Ge.
Source:IOPscience
Ge selective epitaxial growth (SEG) in shallow trench isolated windows is of great interest in advanced devices due to the good lateral electrical isolation of shallow trenches and the possibility of integrating Ge on Si wafers. However, the high density of threading dislocations in strain-relaxed Ge layers and facet formation are two major concerns in Ge SEG. In this work, we have obtained facet-free growth of Ge in shallow trench isolated Si windows with a threading dislocation density (TDD) of 4.2×108 cm-2. A mass transport model is developed to simulate the Ge faceting and the factors influencing the Ge deposition selectivity are studied.
Source:IOPscience
We investigate the high-temperature characteristics of wafer-bonded silicon-on-insulator (SOI)-based Ge film with two different intermediate bonding layers. For an amorphous Ge (a-Ge) bonding layer, due to the crystallization of a-Ge, many gas bubbles appear at the bonded interface to form Ge pits on the SOI. When the wafer pairs are annealed at ≥400 °C, new gas bubbles appear and merge, leading to cracking of the Ge film due to the fact that the new gas bubbles cannot be transferred sufficiently rapidly out of the bonded interface of two single-crystal materials. For an a-Ge/a-Si bonding layer, the porous a-Si can serve as a reservoir at the bonded interface to absorb the by-products. With increase in a-Si layer thickness, the gas bubble density decreases. New gas bubbles are not observed after annealing at 500 °C when a 30 nm thick a-Si layer is introduced. More importantly, the quality of the Ge film with an a-Ge/a-Si bonding layer significantly improves after post-annealing. This can be explained by the repair of the point defects and restraining of the nucleation of threading dislocations by a-Si (no crystal orientation). This work presents high-quality heterogeneous hybrid integration of photoelectric materials by wafer bonding, which may give guidance for the low-temperature integration of Ge/Si, GeSn/Si and III–V/Si.
Source:IOPscience
Two-dimensional (2D) arrays of nanometre scale holes were opened in thin SiO2 layers on silicon by electron beam lithography and chemical etching. Oxidized silicon wafers with a 5 nm thick SiO2 layer on top were used in this respect. Pattern transfer involved either only removal of SiO2 or a two-step process of oxide removal and anisotropic silicon chemical etching to form nanometre scale silicon V-grooves. The size of the holes in the photoresist layer varied in the range 40–80 nm, depending on the exposure dose used. The smallest holes in the oxide were about 50 nm in diameter, while in V-grooves the smallest width was nm. 2D arrays of Ge dots or Ge/Si hetero-nanocrystals were selectively grown on these patterned silicon wafers. In small windows only one Ge island per hole was nucleated.
Source:IOPscience
High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. By plan view TEM it is shown, that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] or equivalent direction. The resulting Ge grown toward [010] direction contains no dislocations. A root mean square of roughness of ~0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.
Source:IOPscience
Ge/SiO2 direct wafer bonding by O2-plasma pretreatment was investigated. The bonding interfaces of Ge/SiO2 low temperature direct wafer bonding were characterized by transmission electron microscopy. The perfectly atomic level Ge/SiO2 bonding was achieved after a 1500C annealing for 60 hours. The excessive O2-plasma exposure resulted in micro-crack formation close to the bonding interface in Ge. A model involved micro-crack formed in Ge was proposed. Our experiments, for the first time, demonstrated that a perfectly seamless bonding of Ge/SiO2 by O2-plasma pretreatment depends not only on optimal O2-plasma pretreatment time but also on the manner of the raised annealing temperature to enhance the bonding strength. A slowly ramping rate heating is crucial to accomplish perfectly seamless Ge/SiO2 wafer bonding apart from an optimal O2-plasma exposure time chosen.
Source:IOPscience
One of the ultimate CMOS structures can be the combination of III-V nMOSFETs and Ge pMOSFETs. In this presentation, we focus on the possible solutions for realizing CMOS integration of III-V and Ge MOSFETs. In order to realize the integration of III-V/Ge MOSFETs, the direct wafer bonding is a promising way. The gate stack formation is also a critical issue for III-V/Ge CMOS integration. We have employed Al2O3 gate insulators for both InGaAs and Ge MOSFETs. We have recently realized Al2O3/GeOx/Ge MOS gate stacks with low Dit and thin EOT by employing ALD Al2O3 and successive plasma oxidation. We consider that metal S/D scheme can be the best solution for III-V/Ge CMOS. We have implemented Ni-based metal S/D technologies for InGaAs and Ge MOSFETs. By employing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.
Source:IOPscience
Effects of trace levels of Ge transferred to Si surfaces during thermal processing of SiGe wafers are presented here. Si wafers were coprocessed in an oxidation furnace with SiGe relaxed graded buffer layers grown on Si. Total X-ray fluorescence measurements on Si wafers showed Ge concentrations in varying degrees depending on oxidation temperature, time, and the number of coprocessed SiGe wafers. The Ge concentration level increases with increase of oxidation time, temperature, and SiGe wafer quantity. It was also observed that the furnace shows "memory" of the process during subsequent process runs. A chlorine-based purge of the oxidation tube after processing SiGe wafers helps reduce the Ge concentration remarkably. Metal oxide semiconductor capacitance and gate leakage characterization were used to evaluate the effects of transferred Ge on the gate oxide. The interface state density is marginally higher on Si wafers with transferred Ge. © 2003 The Electrochemical Society. All rights reserved.
Source:IOPscience
The technical potential of room temperature bonding of wafers in vacuum using amorphous Si (a-Si) and Ge (a-Ge) films was studied. Transmission electron microscopy images revealed no interface corresponding to the original films surfaces for bonded a–Ge–a–Ge films. Analyses of film structure and the surface free energy at the bonded interface revealed higher bonding potential at the connected a–Ge–a–Ge interface than that of a–Si films. The electrical resistivity of a-Ge films is 0.62 Ωm, which is lower than that of a-Si film (4.7 Ωm), but 7–8 order higher than that of representative material films used for bonding in vacuum. Our results indicate that room temperature bonding using a–Ge films is useful to bond wafers without any marked influence on the electrical properties of devices on wafer surfaces caused by the electrical conductivity of films used for bonding.
Source:IOPscience
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