2020年2月19日星期三

The Characteristics of Interface Microstructures in Germanium/SiO2 Low Temperature Wafer Bonding

Ge/SiO2 direct wafer bonding by O2-plasma pretreatment was investigated. The bonding interfaces of Ge/SiO2 low temperature direct wafer bonding were characterized by transmission electron microscopy. The perfectly atomic level Ge/SiO2 bonding was achieved after a 1500C annealing for 60 hours. The excessive O2-plasma exposure resulted in micro-crack formation close to the bonding interface in Ge. A model involved micro-crack formed in Ge was proposed. Our experiments, for the first time, demonstrated that a perfectly seamless bonding of Ge/SiO2 by O2-plasma pretreatment depends not only on optimal O2-plasma pretreatment time but also on the manner of the raised annealing temperature to enhance the bonding strength. A slowly ramping rate heating is crucial to accomplish perfectly seamless Ge/SiO2 wafer bonding apart from an optimal O2-plasma exposure time chosen.

Source:IOPscience

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2020年2月12日星期三

(Invited) Device and Integration Technologies of III-V/Ge Channel CMOS

One of the ultimate CMOS structures can be the combination of III-V nMOSFETs and Ge pMOSFETs. In this presentation, we focus on the possible solutions for realizing CMOS integration of III-V and Ge MOSFETs. In order to realize the integration of III-V/Ge MOSFETs, the direct wafer bonding is a promising way. The gate stack formation is also a critical issue for III-V/Ge CMOS integration. We have employed Al2O3 gate insulators for both InGaAs and Ge MOSFETs. We have recently realized Al2O3/GeOx/Ge MOS gate stacks with low Dit and thin EOT by employing ALD Al2O3 and successive plasma oxidation. We consider that metal S/D scheme can be the best solution for III-V/Ge CMOS. We have implemented Ni-based metal S/D technologies for InGaAs and Ge MOSFETs. By employing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

Source:IOPscience

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2020年1月20日星期一

Analysis of Trace Levels of Ge Transferred to Si Wafer Surfaces during SiGe Wafer Processing

Effects of trace levels of Ge transferred to Si surfaces during thermal processing of SiGe wafers are presented here. Si wafers were coprocessed in an oxidation furnace with SiGe relaxed graded buffer layers grown on Si. Total X-ray fluorescence measurements on Si wafers showed Ge concentrations in varying degrees depending on oxidation temperature, time, and the number of coprocessed SiGe wafers. The Ge concentration level increases with increase of oxidation time, temperature, and SiGe wafer quantity. It was also observed that the furnace shows "memory" of the process during subsequent process runs. A chlorine-based purge of the oxidation tube after processing SiGe wafers helps reduce the Ge concentration remarkably. Metal oxide semiconductor capacitance and gate leakage characterization were used to evaluate the effects of transferred Ge on the gate oxide. The interface state density is marginally higher on Si wafers with transferred Ge. © 2003 The Electrochemical Society. All rights reserved.

Source:IOPscience

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2020年1月13日星期一

Room Temperature Bonding of Wafers Using Si and Ge Films with Extremely Low Electrical Conductivity

The technical potential of room temperature bonding of wafers in vacuum using amorphous Si (a-Si) and Ge (a-Ge) films was studied. Transmission electron microscopy images revealed no interface corresponding to the original films surfaces for bonded a–Ge–a–Ge films. Analyses of film structure and the surface free energy at the bonded interface revealed higher bonding potential at the connected a–Ge–a–Ge interface than that of a–Si films. The electrical resistivity of a-Ge films is 0.62 Ωm, which is lower than that of a-Si film (4.7 Ωm), but 7–8 order higher than that of representative material films used for bonding in vacuum. Our results indicate that room temperature bonding using a–Ge films is useful to bond wafers without any marked influence on the electrical properties of devices on wafer surfaces caused by the electrical conductivity of films used for bonding.

Source:IOPscience

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