Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, etch pit density (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B2O3 encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, lattice parameter, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are in contrast to a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters.] Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at firstname.lastname@example.org and email@example.com
The dependence of the morphology and crystallinity of an amorphous Ge (a-Ge) interlayer between two Si wafers on the annealing temperature is identified to understand the bubble evolution mechanism. The effect of a-Ge layer thickness on the bubble density and size at different annealing temperatures is also clearly clarified. It suggests that the bubble density is significantly affected by the crystallinity and thickness of the a-Ge layer. With the increase of the crystallinity and thickness of the a-Ge layer, the bubble density decreases. It is important that a near-bubble-free Ge interface, which is also an oxide-free interface, is achieved when the bonded Si wafers (a-Gelayer thickness ≥ 20 nm) are annealed at 400 °C. Furthermore, the crystallization temperature of the a-Ge between the bonded Si wafers is lower than that on a Si substrate alone and the Ge grains firstly form at the Ge/Ge bonded interface, rather than the Ge/Si interface. We believe that the stress-induced crystallization of a-Ge film and the intermixing of Ge atoms at the Ge/Ge interface can be responsible for this feature. Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at firstname.lastname@example.org and email@example.com
We present a novel process for integrating germanium with silicon-on-insulator (SOI) wafers. Germanium is implanted into SOI which is then oxidized, trapping the germanium between the two oxide layers (the grown oxide and the buried oxide). With careful control of the implantation and oxidation conditions this process creates a thin layer (current experiments indicate up to 20-30nm) of almost pure germanium. The layer can be used potentially for fabrication of integrated photo-detectors sensitive to infrared wavelengths, or may serve as a seed for further germanium growth. Results are presented from electron microscopy and Rutherford back-scattering analysis, as well as preliminary modelling using an analytical description of the process. Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at firstname.lastname@example.org and email@example.com
We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.