GE Wafer: 五月 2018

2018年5月15日星期二

Tensile strain engineering of germanium micro-disks on free-standing SiO2 beams

Tensile strain is required to enhance light-emitting direct-gap recombinations in germanium (Ge), which is a promising group IV material for realizing a monolithic light source on Si. Ge micro-disks on free-standing SiO2 beams were fabricated using Ge-on-Insulator wafers for applying tensile strain to Ge in a structure compatible with an optical confinement. We have studied the nature of the strain by Raman spectroscopy in comparison with finite-element computer simulations. We show the impacts of the beam design on the corresponding strain value, orientation, and uniformity, which can be exploited for Ge light emission applications. It was found that the tensile strain values are larger if the length of the beam is smaller. We confirmed that both uniaxial and biaxial strain can be applied to Ge disks, and maximum strain values of 1.1 and 0.6% have been achieved, as confirmed by Raman spectroscopy. From the photoluminescence spectra of Ge micro-disks, we have also found a larger energy-splitting between the light-hole and the heavy-hole bands in shorter beams, indicating the impact of tensile strain.

Source:IOPscience

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2018年5月8日星期二

III–V/Ge channel MOS device technologies in nano CMOS era

CMOS utilizing high-mobility III–V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III–V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III–V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III–V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III–V MOS device technologies, we mainly address the gate stack technology, III–V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III–V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III–V/Ge channels.