2019年12月25日星期三

(Invited) Significant Enhancement of High-Ns Electron Mobility in Ge n-MOSFETs with Atomically Flat Ge/GeO2 Interface

The rapid degradation of high-Ns electron mobility in Ge n-MOSFETs is still one of the greatest concerns in Ge CMOS technology. Although there are many possible origins so far considered, the degradation mechanism is still unclear in spite of its importance. In this work, we clarify wafer-related origins for electron mobility degradation in Ge n-MOSFETs. High-Ns electron mobility is dramatically improved thanks to (i) atomically flat Ge surface formation, followed by (ii) layer-by-layer oxidation. (iii) Oxygen-related neutral impurities in Ge substrates could be another origin of the mobility reduction on Ge wafers. By successfully eliminating these scattering sources in Ge n-MOSFETs, we demonstrate intrinsically high electron mobility in a wide range of Ns.

Source:IOPscience

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2019年12月11日星期三

Interface characteristics and electrical transport of Ge/Si heterojunction fabricated by low-temperature wafer bonding

We report a promising method for oxide-layer-free germanium (Ge)/silicon (Si) wafer bonding based on an amorphous Ge (a-Ge) intermediate layer between Si and Ge wafers. The effect of the exposure time (t e), during which the a-Ge is exposed to the air after sputtering and being taken out of the chamber on the bubble density at the bonded interface, is identified and a near-bubble-free Ge/Si bonded interface is achieved for the t e of 3 s. The crystallization of a-Ge at Ge/Si bonded interface starts from a-Ge/Ge interface and it fully turns to be single-crystal Ge after post-annealing. The oxide layer at a-Ge/a-Ge bonded interface formed by the interface hydrophilic reaction disappears due to the atom redistribution triggered by the crystallization of a-Ge. As expected, the performance of the Ge/Si heterojunction diode is significantly improved by this oxide-layer-free Ge/Si bonded interface. A low dark current of 1.6 µA, high on/off current ratio of 3.4  ×  105, and low ideality factor of 1.02 (150 K) is achieved at  −0.5 V for the bonded Ge/Si diode. Finally, the carrier transport mechanisms at Ge/Si bonded interface annealed at different temperatures are also clearly clarified.

Source:IOPscience
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2019年12月4日星期三

300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut™ Technology

We have fabricated 300 mm Si0.3Ge0.7-On-Insulator substrates with the SmartCutTM approach. The donor wafers consisted in polished, 5 µm thick Si0.3Ge0.7 Strain-Relaxed Buffers (SRBs) on top of Si(001) substrates. The following stacks were deposited on top of those SRBs: (low Ge content SiGe / Si0.3Ge0.7) bilayers and (low Ge content SiGe / Si0.3Ge0.7 / low Ge content SiGe / Si0.3Ge0.7) multilayers. The thin, low Ge content SiGe layers were used as etch stops during the fabrication of the SiGeOI wafers and (in the second case) for the re-use of the expensive SRBs. A slight surface resurgence of the surface cross-hatch occurred as the deposited thicknesses became higher. The Ge content in the epitaxial layers was otherwise closely matched to that in the SRBs (70% instead of 68%) and some O peaks present at the Si0.3Ge0.7 / low Ge content SiGe interfaces. After H+ ion implantation, bonding and splitting, a SC1 solution was used to etch the Si0.3Ge0.7 layers and stop on the low Ge content SiGe layers. Meanwhile, TMAH was used in order to etch the low Ge content SiGe layers and stop on the Si0.3Ge0.7 layers. We obtained in the end 57 nm thick, flat Si0.3Ge0.7 layers (7.4 nm range) on top of the buried oxide (root mean square roughness: 0.3 nm only).

Source:IOPscience
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